Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	29178	0	0
entropy_period_rd_A	2147483647	1446	0	0
intr_enable_rd_A	2147483647	1858	0	0
prefix_0_rd_A	2147483647	1359	0	0
prefix_10_rd_A	2147483647	1324	0	0
prefix_1_rd_A	2147483647	1269	0	0
prefix_2_rd_A	2147483647	1321	0	0
prefix_3_rd_A	2147483647	1338	0	0
prefix_4_rd_A	2147483647	1190	0	0
prefix_5_rd_A	2147483647	1273	0	0
prefix_6_rd_A	2147483647	1379	0	0
prefix_7_rd_A	2147483647	1302	0	0
prefix_8_rd_A	2147483647	1197	0	0
prefix_9_rd_A	2147483647	1250	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	29178	0	0
T50	161054	25803	0	0
T51	0	37	0	0
T52	0	139	0	0
T121	0	264	0	0
T122	0	1	0	0
T123	0	1	0	0
T126	0	51	0	0
T129	0	241	0	0
T135	0	1	0	0
T137	0	6	0	0
T139	135696	0	0	0
T140	5939	0	0	0
T141	72034	0	0	0
T142	979012	0	0	0
T143	507105	0	0	0
T144	30987	0	0	0
T145	973256	0	0	0
T146	507714	0	0	0
T147	645546	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1446	0	0
T97	2097	2	0	0
T100	11383	64	0	0
T102	8276	11	0	0
T105	13070	73	0	0
T157	125748	125	0	0
T158	1827	3	0	0
T159	9466	41	0	0
T160	2619	3	0	0
T161	2101	6	0	0
T162	2838	12	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1858	0	0
T100	11383	6	0	0
T102	8276	12	0	0
T128	1351	29	0	0
T157	125748	278	0	0
T158	1827	1	0	0
T159	9466	17	0	0
T160	2619	26	0	0
T163	1412	30	0	0
T164	1451	14	0	0
T165	1704	13	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1359	0	0
T97	2097	3	0	0
T100	11383	44	0	0
T102	8276	17	0	0
T105	13070	62	0	0
T138	4570	15	0	0
T157	125748	312	0	0
T158	1827	8	0	0
T159	9466	24	0	0
T161	2101	2	0	0
T162	2838	6	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1324	0	0
T100	11383	9	0	0
T102	8276	13	0	0
T105	13070	63	0	0
T157	125748	297	0	0
T158	1827	1	0	0
T159	9466	16	0	0
T160	2619	9	0	0
T161	2101	8	0	0
T162	2838	3	0	0
T166	21134	49	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1269	0	0
T100	11383	40	0	0
T102	8276	18	0	0
T105	13070	49	0	0
T138	4570	13	0	0
T157	125748	289	0	0
T158	1827	8	0	0
T159	9466	21	0	0
T160	2619	3	0	0
T162	2838	10	0	0
T166	21134	40	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1321	0	0
T97	2097	1	0	0
T100	11383	38	0	0
T102	8276	22	0	0
T105	13070	67	0	0
T131	10883	6	0	0
T157	125748	273	0	0
T159	9466	22	0	0
T160	2619	10	0	0
T161	2101	7	0	0
T162	2838	5	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1338	0	0
T100	11383	18	0	0
T102	8276	11	0	0
T105	13070	67	0	0
T157	125748	283	0	0
T158	1827	2	0	0
T159	9466	22	0	0
T160	2619	8	0	0
T161	2101	7	0	0
T162	2838	10	0	0
T166	21134	64	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1190	0	0
T97	2097	1	0	0
T100	11383	24	0	0
T102	8276	14	0	0
T105	13070	54	0	0
T157	125748	209	0	0
T158	1827	4	0	0
T159	9466	17	0	0
T160	2619	14	0	0
T161	2101	4	0	0
T162	2838	9	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1273	0	0
T100	11383	68	0	0
T102	8276	16	0	0
T105	13070	74	0	0
T138	4570	3	0	0
T157	125748	276	0	0
T158	1827	4	0	0
T159	9466	28	0	0
T160	2619	6	0	0
T162	2838	7	0	0
T166	21134	44	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1379	0	0
T97	2097	4	0	0
T100	11383	98	0	0
T102	8276	13	0	0
T105	13070	60	0	0
T138	4570	3	0	0
T157	125748	294	0	0
T159	9466	49	0	0
T160	2619	6	0	0
T161	2101	1	0	0
T162	2838	7	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1302	0	0
T97	2097	2	0	0
T100	11383	5	0	0
T102	8276	13	0	0
T105	13070	56	0	0
T138	4570	7	0	0
T157	125748	284	0	0
T158	1827	9	0	0
T159	9466	40	0	0
T160	2619	11	0	0
T161	2101	1	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1197	0	0
T100	11383	15	0	0
T102	8276	4	0	0
T105	13070	65	0	0
T113	11138	22	0	0
T157	125748	239	0	0
T158	1827	4	0	0
T159	9466	15	0	0
T160	2619	4	0	0
T162	2838	5	0	0
T166	21134	36	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1250	0	0
T100	11383	39	0	0
T102	8276	19	0	0
T105	13070	79	0	0
T138	4570	14	0	0
T157	125748	234	0	0
T158	1827	3	0	0
T159	9466	24	0	0
T160	2619	1	0	0
T161	2101	9	0	0
T162	2838	11	0	0