Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

254814414

1

T1

17050

T2

693

T3

3457

full_word

200345833

1

T1

244420

T2

1429

T3

4790

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	455159927	1			T1	261470		T2	2122		T3	8247
auto[TlIntgErrCmd]	106	1			T99	8		T100	4		T101	3
auto[TlIntgErrData]	112	1			T99	6		T100	10		T101	5
auto[TlIntgErrBoth]	102	1			T99	6		T100	6		T101	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

239972158

1

T1

68382

T2

1105

T3

5546

auto[1]

215188089

1

T1

193088

T2

1017

T3

2701

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	152778323	1			T1	14235		T2	402		T3	2148
auto[TlIntgErrNone]	partial	auto[1]	102035797	1			T1	2815		T2	291		T3	1309
auto[TlIntgErrNone]	full_word	auto[0]	87193694	1			T1	54147		T2	703		T3	3398
auto[TlIntgErrNone]	full_word	auto[1]	113152113	1			T1	190273		T2	726		T3	1392
auto[TlIntgErrCmd]	partial	auto[0]	41	1			T99	4		T100	1		T101	1
auto[TlIntgErrCmd]	partial	auto[1]	55	1			T99	3		T100	3		T101	1
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T101	1		T164	1		T166	1
auto[TlIntgErrCmd]	full_word	auto[1]	7	1			T99	1		T161	2		T167	1
auto[TlIntgErrData]	partial	auto[0]	50	1			T99	4		T100	4		T101	2
auto[TlIntgErrData]	partial	auto[1]	53	1			T99	2		T100	5		T101	1
auto[TlIntgErrData]	full_word	auto[0]	7	1			T100	1		T101	2		T164	1
auto[TlIntgErrData]	full_word	auto[1]	2	1			T161	1		T167	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	36	1			T99	1		T100	3		T101	2
auto[TlIntgErrBoth]	partial	auto[1]	59	1			T99	5		T100	3		T160	5
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T164	1		T166	1		T168	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T160	1		T164	1		T161	1