Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	71712	0	0
entropy_period_rd_A	2147483647	2631	0	0
intr_enable_rd_A	2147483647	3790	0	0
prefix_0_rd_A	2147483647	2744	0	0
prefix_10_rd_A	2147483647	2763	0	0
prefix_1_rd_A	2147483647	2886	0	0
prefix_2_rd_A	2147483647	2712	0	0
prefix_3_rd_A	2147483647	2747	0	0
prefix_4_rd_A	2147483647	2903	0	0
prefix_5_rd_A	2147483647	2708	0	0
prefix_6_rd_A	2147483647	2842	0	0
prefix_7_rd_A	2147483647	2836	0	0
prefix_8_rd_A	2147483647	2827	0	0
prefix_9_rd_A	2147483647	2664	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	71712	0	0
T31	4162	0	0	0
T44	137120	18809	0	0
T45	0	23978	0	0
T46	0	25992	0	0
T99	0	3	0	0
T100	0	2	0	0
T105	0	227	0	0
T106	0	1	0	0
T107	0	27	0	0
T108	0	237	0	0
T109	0	62	0	0
T110	34346	0	0	0
T111	51436	0	0	0
T112	170702	0	0	0
T113	341632	0	0	0
T114	24524	0	0	0
T115	187050	0	0	0
T116	332200	0	0	0
T117	132988	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2631	0	0
T45	265670	53	0	0
T46	0	86	0	0
T81	0	17	0	0
T94	0	49	0	0
T96	0	80	0	0
T130	0	418	0	0
T131	0	5	0	0
T132	0	3	0	0
T133	0	22	0	0
T134	0	8	0	0
T135	405002	0	0	0
T136	488477	0	0	0
T137	15761	0	0	0
T138	875550	0	0	0
T139	706394	0	0	0
T140	615091	0	0	0
T141	180557	0	0	0
T142	185683	0	0	0
T143	135662	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3790	0	0
T45	265670	70	0	0
T46	0	56	0	0
T81	0	17	0	0
T96	0	84	0	0
T103	0	16	0	0
T130	0	412	0	0
T131	0	7	0	0
T132	0	7	0	0
T133	0	42	0	0
T135	405002	0	0	0
T136	488477	0	0	0
T137	15761	0	0	0
T138	875550	0	0	0
T139	706394	0	0	0
T140	615091	0	0	0
T141	180557	0	0	0
T142	185683	0	0	0
T143	135662	0	0	0
T144	0	14	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2744	0	0
T45	265670	56	0	0
T46	0	49	0	0
T81	0	2	0	0
T94	0	18	0	0
T96	0	40	0	0
T130	0	414	0	0
T131	0	5	0	0
T132	0	12	0	0
T133	0	82	0	0
T134	0	8	0	0
T135	405002	0	0	0
T136	488477	0	0	0
T137	15761	0	0	0
T138	875550	0	0	0
T139	706394	0	0	0
T140	615091	0	0	0
T141	180557	0	0	0
T142	185683	0	0	0
T143	135662	0	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2763	0	0
T45	265670	63	0	0
T46	0	78	0	0
T81	0	8	0	0
T94	0	32	0	0
T96	0	46	0	0
T130	0	429	0	0
T131	0	9	0	0
T132	0	5	0	0
T133	0	8	0	0
T134	0	1	0	0
T135	405002	0	0	0
T136	488477	0	0	0
T137	15761	0	0	0
T138	875550	0	0	0
T139	706394	0	0	0
T140	615091	0	0	0
T141	180557	0	0	0
T142	185683	0	0	0
T143	135662	0	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2886	0	0
T45	265670	72	0	0
T46	0	88	0	0
T81	0	20	0	0
T94	0	27	0	0
T96	0	49	0	0
T130	0	425	0	0
T131	0	8	0	0
T132	0	4	0	0
T133	0	25	0	0
T134	0	8	0	0
T135	405002	0	0	0
T136	488477	0	0	0
T137	15761	0	0	0
T138	875550	0	0	0
T139	706394	0	0	0
T140	615091	0	0	0
T141	180557	0	0	0
T142	185683	0	0	0
T143	135662	0	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2712	0	0
T45	265670	50	0	0
T46	0	76	0	0
T81	0	8	0	0
T88	0	16	0	0
T94	0	36	0	0
T96	0	56	0	0
T130	0	469	0	0
T132	0	3	0	0
T133	0	46	0	0
T134	0	6	0	0
T135	405002	0	0	0
T136	488477	0	0	0
T137	15761	0	0	0
T138	875550	0	0	0
T139	706394	0	0	0
T140	615091	0	0	0
T141	180557	0	0	0
T142	185683	0	0	0
T143	135662	0	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2747	0	0
T45	265670	59	0	0
T46	0	91	0	0
T81	0	9	0	0
T94	0	47	0	0
T96	0	43	0	0
T130	0	512	0	0
T131	0	8	0	0
T132	0	7	0	0
T133	0	11	0	0
T134	0	4	0	0
T135	405002	0	0	0
T136	488477	0	0	0
T137	15761	0	0	0
T138	875550	0	0	0
T139	706394	0	0	0
T140	615091	0	0	0
T141	180557	0	0	0
T142	185683	0	0	0
T143	135662	0	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2903	0	0
T45	265670	67	0	0
T46	0	65	0	0
T81	0	9	0	0
T94	0	25	0	0
T96	0	41	0	0
T130	0	438	0	0
T131	0	4	0	0
T132	0	14	0	0
T133	0	7	0	0
T134	0	1	0	0
T135	405002	0	0	0
T136	488477	0	0	0
T137	15761	0	0	0
T138	875550	0	0	0
T139	706394	0	0	0
T140	615091	0	0	0
T141	180557	0	0	0
T142	185683	0	0	0
T143	135662	0	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2708	0	0
T45	265670	58	0	0
T46	0	86	0	0
T81	0	12	0	0
T88	0	9	0	0
T94	0	32	0	0
T96	0	57	0	0
T130	0	390	0	0
T131	0	5	0	0
T132	0	10	0	0
T134	0	1	0	0
T135	405002	0	0	0
T136	488477	0	0	0
T137	15761	0	0	0
T138	875550	0	0	0
T139	706394	0	0	0
T140	615091	0	0	0
T141	180557	0	0	0
T142	185683	0	0	0
T143	135662	0	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2842	0	0
T45	265670	56	0	0
T46	0	60	0	0
T81	0	13	0	0
T94	0	29	0	0
T96	0	54	0	0
T130	0	388	0	0
T131	0	1	0	0
T132	0	7	0	0
T133	0	31	0	0
T134	0	6	0	0
T135	405002	0	0	0
T136	488477	0	0	0
T137	15761	0	0	0
T138	875550	0	0	0
T139	706394	0	0	0
T140	615091	0	0	0
T141	180557	0	0	0
T142	185683	0	0	0
T143	135662	0	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2836	0	0
T45	265670	98	0	0
T46	0	51	0	0
T81	0	11	0	0
T88	0	4	0	0
T94	0	20	0	0
T96	0	46	0	0
T130	0	440	0	0
T132	0	19	0	0
T133	0	28	0	0
T134	0	6	0	0
T135	405002	0	0	0
T136	488477	0	0	0
T137	15761	0	0	0
T138	875550	0	0	0
T139	706394	0	0	0
T140	615091	0	0	0
T141	180557	0	0	0
T142	185683	0	0	0
T143	135662	0	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2827	0	0
T45	265670	93	0	0
T46	0	79	0	0
T81	0	3	0	0
T94	0	46	0	0
T96	0	29	0	0
T130	0	477	0	0
T131	0	9	0	0
T132	0	10	0	0
T133	0	13	0	0
T134	0	1	0	0
T135	405002	0	0	0
T136	488477	0	0	0
T137	15761	0	0	0
T138	875550	0	0	0
T139	706394	0	0	0
T140	615091	0	0	0
T141	180557	0	0	0
T142	185683	0	0	0
T143	135662	0	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2664	0	0
T45	265670	61	0	0
T46	0	65	0	0
T81	0	9	0	0
T94	0	12	0	0
T96	0	45	0	0
T130	0	465	0	0
T131	0	2	0	0
T132	0	5	0	0
T133	0	21	0	0
T134	0	1	0	0
T135	405002	0	0	0
T136	488477	0	0	0
T137	15761	0	0	0
T138	875550	0	0	0
T139	706394	0	0	0
T140	615091	0	0	0
T141	180557	0	0	0
T142	185683	0	0	0
T143	135662	0	0	0