Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

255429161

1

T1

2301

T2

541

T3

421

full_word

199785333

1

T1

4867

T2

1446

T3

1109

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	455214224	1			T1	7168		T2	1987		T3	1530
auto[TlIntgErrCmd]	79	1			T117	5		T118	5		T119	6
auto[TlIntgErrData]	98	1			T117	3		T118	3		T119	6
auto[TlIntgErrBoth]	93	1			T117	2		T118	12		T119	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

239995552

1

T1

4914

T2

1035

T3

1105

auto[1]

215218942

1

T1

2254

T2

952

T3

425

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	152984917	1			T1	1423		T2	335		T3	276
auto[TlIntgErrNone]	partial	auto[1]	102443997	1			T1	878		T2	206		T3	145
auto[TlIntgErrNone]	full_word	auto[0]	87010517	1			T1	3491		T2	700		T3	829
auto[TlIntgErrNone]	full_word	auto[1]	112774793	1			T1	1376		T2	746		T3	280
auto[TlIntgErrCmd]	partial	auto[0]	24	1			T117	1		T119	1		T138	1
auto[TlIntgErrCmd]	partial	auto[1]	49	1			T117	4		T118	5		T119	5
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T138	1		T154	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T141	1		T127	1		T182	1
auto[TlIntgErrData]	partial	auto[0]	52	1			T118	2		T119	2		T138	2
auto[TlIntgErrData]	partial	auto[1]	36	1			T117	3		T118	1		T119	4
auto[TlIntgErrData]	full_word	auto[0]	5	1			T183	1		T181	2		T184	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T138	1		T184	1		T185	1
auto[TlIntgErrBoth]	partial	auto[0]	33	1			T118	3		T119	4		T141	3
auto[TlIntgErrBoth]	partial	auto[1]	53	1			T117	2		T118	8		T119	3
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T127	1		T181	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T118	1		T119	1		T138	1