Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	133034	0	0
entropy_period_rd_A	2147483647	2061	0	0
intr_enable_rd_A	2147483647	3234	0	0
prefix_0_rd_A	2147483647	2354	0	0
prefix_10_rd_A	2147483647	2311	0	0
prefix_1_rd_A	2147483647	2489	0	0
prefix_2_rd_A	2147483647	2262	0	0
prefix_3_rd_A	2147483647	2225	0	0
prefix_4_rd_A	2147483647	2334	0	0
prefix_5_rd_A	2147483647	2377	0	0
prefix_6_rd_A	2147483647	2360	0	0
prefix_7_rd_A	2147483647	2347	0	0
prefix_8_rd_A	2147483647	2280	0	0
prefix_9_rd_A	2147483647	2303	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	133034	0	0
T57	444438	26590	0	0
T58	0	76157	0	0
T59	0	27125	0	0
T118	0	6	0	0
T123	0	2	0	0
T124	0	144	0	0
T125	0	2	0	0
T126	0	4	0	0
T129	1723	0	0	0
T130	17563	0	0	0
T131	306371	0	0	0
T132	34522	0	0	0
T133	934321	0	0	0
T134	293425	0	0	0
T135	18463	0	0	0
T136	43442	0	0	0
T137	56875	0	0	0
T138	0	1	0	0
T141	0	1	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2061	0	0
T57	444438	58	0	0
T98	0	3	0	0
T113	0	35	0	0
T117	0	48	0	0
T118	0	51	0	0
T126	0	17	0	0
T128	0	81	0	0
T129	1723	0	0	0
T130	17563	0	0	0
T131	306371	0	0	0
T132	34522	0	0	0
T133	934321	0	0	0
T134	293425	0	0	0
T135	18463	0	0	0
T136	43442	0	0	0
T137	56875	0	0	0
T154	0	64	0	0
T155	0	121	0	0
T156	0	69	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3234	0	0
T57	444438	58	0	0
T98	0	7	0	0
T117	0	87	0	0
T118	0	76	0	0
T121	0	4	0	0
T126	0	9	0	0
T128	0	134	0	0
T129	1723	0	0	0
T130	17563	0	0	0
T131	306371	0	0	0
T132	34522	0	0	0
T133	934321	0	0	0
T134	293425	0	0	0
T135	18463	0	0	0
T136	43442	0	0	0
T137	56875	0	0	0
T154	0	109	0	0
T157	0	4	0	0
T158	0	27	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2354	0	0
T57	444438	57	0	0
T98	0	13	0	0
T113	0	21	0	0
T117	0	49	0	0
T118	0	41	0	0
T126	0	7	0	0
T128	0	87	0	0
T129	1723	0	0	0
T130	17563	0	0	0
T131	306371	0	0	0
T132	34522	0	0	0
T133	934321	0	0	0
T134	293425	0	0	0
T135	18463	0	0	0
T136	43442	0	0	0
T137	56875	0	0	0
T154	0	59	0	0
T155	0	230	0	0
T156	0	34	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2311	0	0
T57	444438	53	0	0
T98	0	15	0	0
T113	0	7	0	0
T117	0	35	0	0
T118	0	44	0	0
T126	0	17	0	0
T128	0	81	0	0
T129	1723	0	0	0
T130	17563	0	0	0
T131	306371	0	0	0
T132	34522	0	0	0
T133	934321	0	0	0
T134	293425	0	0	0
T135	18463	0	0	0
T136	43442	0	0	0
T137	56875	0	0	0
T154	0	33	0	0
T155	0	207	0	0
T156	0	41	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2489	0	0
T57	444438	64	0	0
T98	0	16	0	0
T113	0	18	0	0
T117	0	24	0	0
T118	0	34	0	0
T126	0	16	0	0
T128	0	58	0	0
T129	1723	0	0	0
T130	17563	0	0	0
T131	306371	0	0	0
T132	34522	0	0	0
T133	934321	0	0	0
T134	293425	0	0	0
T135	18463	0	0	0
T136	43442	0	0	0
T137	56875	0	0	0
T154	0	46	0	0
T155	0	260	0	0
T156	0	53	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2262	0	0
T57	444438	55	0	0
T98	0	15	0	0
T113	0	21	0	0
T117	0	29	0	0
T118	0	53	0	0
T126	0	10	0	0
T128	0	80	0	0
T129	1723	0	0	0
T130	17563	0	0	0
T131	306371	0	0	0
T132	34522	0	0	0
T133	934321	0	0	0
T134	293425	0	0	0
T135	18463	0	0	0
T136	43442	0	0	0
T137	56875	0	0	0
T154	0	39	0	0
T155	0	251	0	0
T156	0	39	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2225	0	0
T57	444438	82	0	0
T98	0	6	0	0
T113	0	8	0	0
T117	0	42	0	0
T118	0	41	0	0
T126	0	15	0	0
T128	0	68	0	0
T129	1723	0	0	0
T130	17563	0	0	0
T131	306371	0	0	0
T132	34522	0	0	0
T133	934321	0	0	0
T134	293425	0	0	0
T135	18463	0	0	0
T136	43442	0	0	0
T137	56875	0	0	0
T154	0	42	0	0
T155	0	210	0	0
T156	0	38	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2334	0	0
T57	444438	43	0	0
T98	0	10	0	0
T113	0	18	0	0
T117	0	47	0	0
T118	0	42	0	0
T126	0	10	0	0
T128	0	83	0	0
T129	1723	0	0	0
T130	17563	0	0	0
T131	306371	0	0	0
T132	34522	0	0	0
T133	934321	0	0	0
T134	293425	0	0	0
T135	18463	0	0	0
T136	43442	0	0	0
T137	56875	0	0	0
T154	0	38	0	0
T155	0	229	0	0
T159	0	4	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2377	0	0
T57	444438	108	0	0
T98	0	14	0	0
T113	0	7	0	0
T117	0	37	0	0
T118	0	38	0	0
T126	0	15	0	0
T128	0	71	0	0
T129	1723	0	0	0
T130	17563	0	0	0
T131	306371	0	0	0
T132	34522	0	0	0
T133	934321	0	0	0
T134	293425	0	0	0
T135	18463	0	0	0
T136	43442	0	0	0
T137	56875	0	0	0
T154	0	30	0	0
T155	0	230	0	0
T156	0	40	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2360	0	0
T57	444438	55	0	0
T98	0	10	0	0
T113	0	4	0	0
T117	0	43	0	0
T118	0	40	0	0
T126	0	16	0	0
T128	0	85	0	0
T129	1723	0	0	0
T130	17563	0	0	0
T131	306371	0	0	0
T132	34522	0	0	0
T133	934321	0	0	0
T134	293425	0	0	0
T135	18463	0	0	0
T136	43442	0	0	0
T137	56875	0	0	0
T154	0	39	0	0
T155	0	216	0	0
T156	0	29	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2347	0	0
T57	444438	59	0	0
T98	0	9	0	0
T113	0	15	0	0
T117	0	35	0	0
T118	0	45	0	0
T126	0	8	0	0
T128	0	82	0	0
T129	1723	0	0	0
T130	17563	0	0	0
T131	306371	0	0	0
T132	34522	0	0	0
T133	934321	0	0	0
T134	293425	0	0	0
T135	18463	0	0	0
T136	43442	0	0	0
T137	56875	0	0	0
T154	0	34	0	0
T155	0	211	0	0
T156	0	54	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2280	0	0
T57	444438	59	0	0
T98	0	7	0	0
T113	0	3	0	0
T117	0	50	0	0
T118	0	51	0	0
T126	0	13	0	0
T128	0	79	0	0
T129	1723	0	0	0
T130	17563	0	0	0
T131	306371	0	0	0
T132	34522	0	0	0
T133	934321	0	0	0
T134	293425	0	0	0
T135	18463	0	0	0
T136	43442	0	0	0
T137	56875	0	0	0
T154	0	53	0	0
T155	0	205	0	0
T156	0	35	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2303	0	0
T57	444438	59	0	0
T98	0	13	0	0
T113	0	15	0	0
T117	0	35	0	0
T118	0	42	0	0
T126	0	16	0	0
T128	0	78	0	0
T129	1723	0	0	0
T130	17563	0	0	0
T131	306371	0	0	0
T132	34522	0	0	0
T133	934321	0	0	0
T134	293425	0	0	0
T135	18463	0	0	0
T136	43442	0	0	0
T137	56875	0	0	0
T154	0	39	0	0
T155	0	227	0	0
T156	0	53	0	0