Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	254594772	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

200879392

1

T1

167

T2

6

T3

266180

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	240657384	1			T1	90		T2	1		T3	105622
values[0x0]	103290713	1			T1	43		T2	3		T3	105550
values[0x1]	111526067	1			T1	54		T2	8		T3	105756

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	198564231	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

256909933

1

T1

175

T2

6

T3

279387

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2060596	1			T3	978		T4	2623		T5	520
valid_sources[0x01]	1517829	1			T3	1095		T4	2583		T5	501
valid_sources[0x02]	1396066	1			T3	989		T4	2590		T5	538
valid_sources[0x03]	1406957	1			T3	879		T4	2617		T5	513
valid_sources[0x04]	1385895	1			T2	1		T3	833		T4	2651
valid_sources[0x05]	1390685	1			T3	2362		T4	2660		T5	527
valid_sources[0x06]	1393757	1			T3	755		T4	2592		T5	376
valid_sources[0x07]	1406348	1			T3	833		T4	2550		T5	549
valid_sources[0x08]	1412492	1			T3	1004		T4	2579		T5	567
valid_sources[0x09]	2272561	1			T2	1		T3	1377		T4	2587
valid_sources[0x0a]	3817829	1			T3	826		T4	2669		T5	540
valid_sources[0x0b]	3165480	1			T3	1928		T4	2659		T5	586
valid_sources[0x0c]	1392442	1			T3	1492		T4	2529		T5	542
valid_sources[0x0d]	1391727	1			T3	2178		T4	2532		T5	544
valid_sources[0x0e]	4693520	1			T3	1689		T4	2556		T5	563
valid_sources[0x0f]	1391028	1			T3	1539		T4	2583		T5	537
valid_sources[0x10]	1478825	1			T3	1085		T4	2627		T5	564
valid_sources[0x11]	1386107	1			T3	897		T4	2572		T5	616
valid_sources[0x12]	1417260	1			T3	1582		T4	2535		T5	515
valid_sources[0x13]	2322639	1			T3	862		T4	2622		T5	544
valid_sources[0x14]	3447685	1			T3	1887		T4	2550		T5	588
valid_sources[0x15]	2055899	1			T3	990		T4	2547		T5	558
valid_sources[0x16]	1514813	1			T3	1739		T4	2591		T5	455
valid_sources[0x17]	1513905	1			T3	881		T4	2666		T5	501
valid_sources[0x18]	1388276	1			T3	921		T4	2541		T5	488
valid_sources[0x19]	3838045	1			T3	1902		T4	2629		T5	539
valid_sources[0x1a]	1392536	1			T2	2		T3	853		T4	2537
valid_sources[0x1b]	1520400	1			T3	999		T4	2555		T5	527
valid_sources[0x1c]	1390666	1			T3	1128		T4	2620		T5	519
valid_sources[0x1d]	3829093	1			T3	961		T4	2552		T5	536
valid_sources[0x1e]	1390262	1			T3	837		T4	2609		T5	456
valid_sources[0x1f]	1405102	1			T3	975		T4	2601		T5	527
valid_sources[0x20]	3865639	1			T3	1681		T4	2531		T5	450
valid_sources[0x21]	1395892	1			T3	3262		T4	2722		T5	634
valid_sources[0x22]	1433557	1			T3	823		T4	2513		T5	531
valid_sources[0x23]	1490566	1			T3	879		T4	2506		T5	580
valid_sources[0x24]	3856958	1			T3	1544		T4	2570		T5	503
valid_sources[0x25]	1395605	1			T3	952		T4	2566		T5	509
valid_sources[0x26]	1388139	1			T3	791		T4	2533		T5	513
valid_sources[0x27]	1524435	1			T3	802		T4	2642		T5	506
valid_sources[0x28]	1469389	1			T3	934		T4	2628		T5	523
valid_sources[0x29]	1390085	1			T3	960		T4	2645		T5	556
valid_sources[0x2a]	1391736	1			T3	2283		T4	2666		T5	530
valid_sources[0x2b]	1393000	1			T3	1876		T4	2537		T5	546
valid_sources[0x2c]	1567242	1			T3	1357		T4	2576		T5	537
valid_sources[0x2d]	1419985	1			T3	897		T4	2586		T5	546
valid_sources[0x2e]	1395681	1			T3	891		T4	2708		T5	481
valid_sources[0x2f]	1392924	1			T3	1043		T4	2594		T5	522
valid_sources[0x30]	1387656	1			T3	2246		T4	2616		T5	520
valid_sources[0x31]	1432895	1			T3	908		T4	2640		T5	509
valid_sources[0x32]	1392048	1			T3	841		T4	2624		T5	532
valid_sources[0x33]	1396683	1			T3	1060		T4	2488		T5	487
valid_sources[0x34]	1391251	1			T3	1201		T4	2550		T5	497
valid_sources[0x35]	1391843	1			T3	1753		T4	2633		T5	542
valid_sources[0x36]	2065099	1			T3	801		T4	2546		T5	558
valid_sources[0x37]	2055259	1			T3	993		T4	2595		T5	513
valid_sources[0x38]	2271720	1			T2	1		T3	998		T4	2639
valid_sources[0x39]	1397889	1			T2	1		T3	1776		T4	2609
valid_sources[0x3a]	1392599	1			T3	1797		T4	2575		T5	524
valid_sources[0x3b]	1396949	1			T3	1155		T4	2688		T5	561
valid_sources[0x3c]	1388830	1			T3	2581		T4	2610		T5	487
valid_sources[0x3d]	1393746	1			T3	1091		T4	2692		T5	524
valid_sources[0x3e]	1847815	1			T3	915		T4	2570		T5	569
valid_sources[0x3f]	3707169	1			T3	1039		T4	2555		T5	464
valid_sources[0x40]	4345660	1			T3	1656		T4	2490		T5	505
valid_sources[0x41]	1400744	1			T2	1		T3	2172		T4	2670
valid_sources[0x42]	2060913	1			T3	1737		T4	2577		T5	572
valid_sources[0x43]	1388777	1			T3	941		T4	2601		T5	530
valid_sources[0x44]	1386743	1			T3	1757		T4	2577		T5	449
valid_sources[0x45]	1389345	1			T3	870		T4	2575		T5	512
valid_sources[0x46]	1390278	1			T3	873		T4	2639		T5	594
valid_sources[0x47]	1389150	1			T3	1063		T4	2564		T5	481
valid_sources[0x48]	2335201	1			T3	811		T4	2603		T5	432
valid_sources[0x49]	1392541	1			T3	888		T4	2643		T5	496
valid_sources[0x4a]	1482846	1			T3	888		T4	2580		T5	483
valid_sources[0x4b]	2053623	1			T3	993		T4	2561		T5	501
valid_sources[0x4c]	1389648	1			T3	1400		T4	2637		T5	537
valid_sources[0x4d]	2302401	1			T3	989		T4	2687		T5	505
valid_sources[0x4e]	1386576	1			T3	1048		T4	2609		T5	508
valid_sources[0x4f]	3939674	1			T3	1626		T4	2501		T5	456
valid_sources[0x50]	1389827	1			T3	939		T4	2577		T5	444
valid_sources[0x51]	1390501	1			T3	800		T4	2602		T5	565
valid_sources[0x52]	3186010	1			T3	987		T4	2632		T5	467
valid_sources[0x53]	1402352	1			T3	2147		T4	2583		T5	494
valid_sources[0x54]	1395449	1			T3	1560		T4	2619		T5	460
valid_sources[0x55]	1519587	1			T3	817		T4	2675		T5	582
valid_sources[0x56]	1400398	1			T3	1815		T4	2568		T5	491
valid_sources[0x57]	3754244	1			T3	1624		T4	2575		T5	549
valid_sources[0x58]	1392611	1			T2	1		T3	949		T4	2556
valid_sources[0x59]	1468443	1			T3	1157		T4	2556		T5	550
valid_sources[0x5a]	3782253	1			T3	1792		T4	2553		T5	458
valid_sources[0x5b]	1389749	1			T3	795		T4	2592		T5	516
valid_sources[0x5c]	1391567	1			T3	1360		T4	2596		T5	574
valid_sources[0x5d]	1399238	1			T3	1108		T4	2641		T5	510
valid_sources[0x5e]	1386126	1			T3	1413		T4	2544		T5	546
valid_sources[0x5f]	2322446	1			T3	1232		T4	2578		T5	498
valid_sources[0x60]	1388187	1			T3	1179		T4	2529		T5	505
valid_sources[0x61]	1870263	1			T3	2195		T4	2641		T5	478
valid_sources[0x62]	2439864	1			T3	928		T4	2539		T5	497
valid_sources[0x63]	2245941	1			T3	1033		T4	2601		T5	576
valid_sources[0x64]	1390493	1			T3	1149		T4	2706		T5	521
valid_sources[0x65]	1386375	1			T3	1398		T4	2629		T5	504
valid_sources[0x66]	1392521	1			T3	1239		T4	2563		T5	584
valid_sources[0x67]	1391629	1			T2	1		T3	1004		T4	2630
valid_sources[0x68]	2175087	1			T2	1		T3	1761		T4	2536
valid_sources[0x69]	1483344	1			T3	1479		T4	2575		T5	550
valid_sources[0x6a]	1386090	1			T3	1255		T4	2554		T5	481
valid_sources[0x6b]	1378700	1			T3	769		T4	2579		T5	476
valid_sources[0x6c]	1389664	1			T3	1645		T4	2679		T5	532
valid_sources[0x6d]	1392099	1			T3	1556		T4	2666		T5	508
valid_sources[0x6e]	1393358	1			T3	812		T4	2603		T5	535
valid_sources[0x6f]	1386220	1			T3	1381		T4	2560		T5	477
valid_sources[0x70]	1391342	1			T3	2675		T4	2681		T5	467
valid_sources[0x71]	1844731	1			T3	830		T4	2544		T5	542
valid_sources[0x72]	1393421	1			T3	803		T4	2624		T5	504
valid_sources[0x73]	1426606	1			T3	1674		T4	2570		T5	520
valid_sources[0x74]	1657145	1			T3	919		T4	2741		T5	528
valid_sources[0x75]	1531775	1			T3	812		T4	2571		T5	574
valid_sources[0x76]	1389978	1			T3	1102		T4	2671		T5	589
valid_sources[0x77]	1389891	1			T3	934		T4	2631		T5	556
valid_sources[0x78]	1380253	1			T3	1071		T4	2632		T5	596
valid_sources[0x79]	1391095	1			T3	807		T4	2619		T5	469
valid_sources[0x7a]	2735566	1			T3	1914		T4	2620		T5	566
valid_sources[0x7b]	1763432	1			T3	980		T4	2575		T5	570
valid_sources[0x7c]	1396576	1			T3	1692		T4	2603		T5	551
valid_sources[0x7d]	1525219	1			T3	1627		T4	2582		T5	558
valid_sources[0x7e]	2315977	1			T3	825		T4	2449		T5	522
valid_sources[0x7f]	2242889	1			T3	1564		T4	2536		T5	494
valid_sources[0x80]	1386754	1			T3	1636		T4	2595		T5	584

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

87687993

1

T1

85

T2

1

T3

57988

values[0x0]

all_enables

biggest_size

60881447

1

T1

40

T2

1

T3

104193

values[0x1]

all_enables

biggest_size

52309952

1

T1

42

T2

4

T3

103999