Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

254913540

1

T1

20

T2

6

T3

50748

full_word

200899771

1

T1

167

T2

6

T3

266180

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	455813021	1			T1	187		T2	12		T3	316928
auto[TlIntgErrCmd]	97	1			T105	8		T106	5		T107	5
auto[TlIntgErrData]	101	1			T105	8		T106	1		T107	4
auto[TlIntgErrBoth]	92	1			T105	4		T106	4		T107	1

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

240718406

1

T1

90

T2

1

T3

105622

auto[1]

215094905

1

T1

97

T2

11

T3

211306

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	153025249	1			T1	5		T3	47634		T4	240656
auto[TlIntgErrNone]	partial	auto[1]	101888032	1			T1	15		T2	6		T3	3114
auto[TlIntgErrNone]	full_word	auto[0]	87693034	1			T1	85		T2	1		T3	57988
auto[TlIntgErrNone]	full_word	auto[1]	113206706	1			T1	82		T2	5		T3	208192
auto[TlIntgErrCmd]	partial	auto[0]	42	1			T105	3		T106	1		T107	1
auto[TlIntgErrCmd]	partial	auto[1]	43	1			T105	4		T106	3		T107	3
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T106	1		T153	1		T155	1
auto[TlIntgErrCmd]	full_word	auto[1]	9	1			T105	1		T107	1		T129	1
auto[TlIntgErrData]	partial	auto[0]	38	1			T105	4		T106	1		T107	2
auto[TlIntgErrData]	partial	auto[1]	52	1			T105	1		T107	2		T129	1
auto[TlIntgErrData]	full_word	auto[0]	3	1			T156	1		T157	1		T158	1
auto[TlIntgErrData]	full_word	auto[1]	8	1			T105	3		T150	2		T155	1
auto[TlIntgErrBoth]	partial	auto[0]	33	1			T105	2		T106	3		T153	2
auto[TlIntgErrBoth]	partial	auto[1]	51	1			T105	2		T106	1		T107	1
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T153	1		T150	1		T158	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T129	1		T159	1		T155	1