Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

253344876

1

T1

164929

T2

631

T3

6156

full_word

199634846

1

T1

195048

T2

3782

T3

12003

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	452979432	1			T1	359977		T2	4413		T3	18159
auto[TlIntgErrCmd]	89	1			T49	6		T103	6		T104	7
auto[TlIntgErrData]	96	1			T49	6		T103	2		T104	8
auto[TlIntgErrBoth]	105	1			T49	8		T103	2		T104	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

239163137

1

T1

218281

T2

3060

T3

12714

auto[1]

213816585

1

T1

141696

T2

1353

T3

5445

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	152150561	1			T1	99419		T2	338		T3	3835
auto[TlIntgErrNone]	partial	auto[1]	101194052	1			T1	65510		T2	293		T3	2321
auto[TlIntgErrNone]	full_word	auto[0]	87012435	1			T1	118862		T2	2722		T3	8879
auto[TlIntgErrNone]	full_word	auto[1]	112622384	1			T1	76186		T2	1060		T3	3124
auto[TlIntgErrCmd]	partial	auto[0]	43	1			T49	2		T103	4		T104	5
auto[TlIntgErrCmd]	partial	auto[1]	38	1			T49	3		T103	1		T104	2
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T103	1		T159	1		T162	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T49	1		T159	1		T163	1
auto[TlIntgErrData]	partial	auto[0]	43	1			T49	3		T104	2		T160	1
auto[TlIntgErrData]	partial	auto[1]	41	1			T49	3		T103	2		T104	5
auto[TlIntgErrData]	full_word	auto[0]	6	1			T160	1		T161	1		T164	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T104	1		T159	1		T162	1
auto[TlIntgErrBoth]	partial	auto[0]	43	1			T49	4		T103	1		T104	3
auto[TlIntgErrBoth]	partial	auto[1]	55	1			T49	4		T103	1		T104	2
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T163	1		T165	1		T166	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T160	2		T167	1		T168	1