Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	3373	0	0
entropy_period_rd_A	2147483647	1042	0	0
intr_enable_rd_A	2147483647	1664	0	0
prefix_0_rd_A	2147483647	1008	0	0
prefix_10_rd_A	2147483647	1127	0	0
prefix_1_rd_A	2147483647	1076	0	0
prefix_2_rd_A	2147483647	1136	0	0
prefix_3_rd_A	2147483647	1073	0	0
prefix_4_rd_A	2147483647	1111	0	0
prefix_5_rd_A	2147483647	1005	0	0
prefix_6_rd_A	2147483647	1122	0	0
prefix_7_rd_A	2147483647	941	0	0
prefix_8_rd_A	2147483647	1109	0	0
prefix_9_rd_A	2147483647	1010	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3373	0	0
T50	5171	1	0	0
T51	4414	98	0	0
T101	4332	10	0	0
T102	3871	105	0	0
T103	13264	2	0	0
T104	8238	2	0	0
T105	3151	200	0	0
T121	6053	4	0	0
T122	6866	2	0	0
T123	3165	4	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1042	0	0
T50	5171	2	0	0
T87	5855	16	0	0
T90	2446	6	0	0
T91	10661	23	0	0
T103	13264	81	0	0
T133	1670	1	0	0
T134	4762	6	0	0
T135	10445	18	0	0
T136	3355	12	0	0
T137	5330	8	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1664	0	0
T50	5171	12	0	0
T87	5855	15	0	0
T90	2446	4	0	0
T91	10661	22	0	0
T103	13264	75	0	0
T112	1119	5	0	0
T133	1670	15	0	0
T134	4762	9	0	0
T135	10445	20	0	0
T136	3355	29	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1008	0	0
T50	5171	14	0	0
T87	5855	24	0	0
T90	2446	3	0	0
T91	10661	17	0	0
T103	13264	42	0	0
T134	4762	7	0	0
T135	10445	30	0	0
T136	3355	8	0	0
T138	9684	11	0	0
T139	2611	7	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1127	0	0
T50	5171	5	0	0
T87	5855	20	0	0
T90	2446	2	0	0
T91	10661	9	0	0
T103	13264	50	0	0
T134	4762	9	0	0
T135	10445	66	0	0
T136	3355	12	0	0
T137	5330	15	0	0
T138	9684	32	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1076	0	0
T50	5171	15	0	0
T87	5855	18	0	0
T90	2446	5	0	0
T91	10661	14	0	0
T103	13264	31	0	0
T135	10445	42	0	0
T136	3355	8	0	0
T137	5330	8	0	0
T138	9684	33	0	0
T139	2611	5	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1136	0	0
T50	5171	8	0	0
T87	5855	19	0	0
T90	2446	11	0	0
T91	10661	24	0	0
T103	13264	34	0	0
T134	4762	14	0	0
T135	10445	80	0	0
T136	3355	4	0	0
T137	5330	20	0	0
T138	9684	43	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1073	0	0
T50	5171	3	0	0
T87	5855	8	0	0
T90	2446	15	0	0
T91	10661	42	0	0
T103	13264	41	0	0
T133	1670	4	0	0
T134	4762	10	0	0
T135	10445	24	0	0
T136	3355	8	0	0
T137	5330	19	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1111	0	0
T50	5171	12	0	0
T87	5855	22	0	0
T90	2446	1	0	0
T91	10661	23	0	0
T103	13264	48	0	0
T133	1670	2	0	0
T134	4762	14	0	0
T135	10445	23	0	0
T136	3355	11	0	0
T137	5330	18	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1005	0	0
T50	5171	4	0	0
T87	5855	17	0	0
T90	2446	11	0	0
T91	10661	20	0	0
T103	13264	48	0	0
T134	4762	23	0	0
T135	10445	43	0	0
T136	3355	10	0	0
T137	5330	4	0	0
T138	9684	16	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1122	0	0
T50	5171	9	0	0
T87	5855	17	0	0
T90	2446	9	0	0
T91	10661	16	0	0
T103	13264	45	0	0
T133	1670	2	0	0
T134	4762	1	0	0
T135	10445	81	0	0
T136	3355	11	0	0
T137	5330	4	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	941	0	0
T50	5171	11	0	0
T87	5855	24	0	0
T90	2446	11	0	0
T91	10661	23	0	0
T103	13264	39	0	0
T134	4762	6	0	0
T135	10445	20	0	0
T136	3355	11	0	0
T137	5330	4	0	0
T138	9684	14	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1109	0	0
T50	5171	11	0	0
T87	5855	11	0	0
T90	2446	6	0	0
T91	10661	38	0	0
T103	13264	31	0	0
T133	1670	2	0	0
T134	4762	43	0	0
T135	10445	20	0	0
T136	3355	11	0	0
T138	9684	4	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1010	0	0
T50	5171	6	0	0
T87	5855	11	0	0
T90	2446	13	0	0
T91	10661	33	0	0
T103	13264	44	0	0
T134	4762	10	0	0
T135	10445	21	0	0
T136	3355	9	0	0
T137	5330	24	0	0
T138	9684	28	0	0