Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

256905480

1

T1

37843

T2

17943

T3

42287

full_word

201041922

1

T1

198056

T2

30703

T3

81047

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	457947082	1			T1	235899		T2	48646		T3	123334
auto[TlIntgErrCmd]	103	1			T107	4		T108	6		T109	6
auto[TlIntgErrData]	109	1			T107	4		T108	1		T109	8
auto[TlIntgErrBoth]	108	1			T107	2		T108	3		T109	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

241795987

1

T1

83329

T2

34493

T3

85465

auto[1]

216151415

1

T1

152570

T2

14153

T3

37869

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	153960510	1			T1	35515		T2	11311		T3	26369
auto[TlIntgErrNone]	partial	auto[1]	102944684	1			T1	2328		T2	6632		T3	15918
auto[TlIntgErrNone]	full_word	auto[0]	87835331	1			T1	47814		T2	23182		T3	59096
auto[TlIntgErrNone]	full_word	auto[1]	113206557	1			T1	150242		T2	7521		T3	21951
auto[TlIntgErrCmd]	partial	auto[0]	33	1			T107	1		T108	1		T109	3
auto[TlIntgErrCmd]	partial	auto[1]	56	1			T107	3		T108	4		T109	2
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T163	1		T166	1		T168	1
auto[TlIntgErrCmd]	full_word	auto[1]	8	1			T108	1		T109	1		T163	1
auto[TlIntgErrData]	partial	auto[0]	51	1			T107	2		T108	1		T109	5
auto[TlIntgErrData]	partial	auto[1]	44	1			T107	1		T109	2		T169	2
auto[TlIntgErrData]	full_word	auto[0]	9	1			T107	1		T109	1		T162	2
auto[TlIntgErrData]	full_word	auto[1]	5	1			T169	1		T164	1		T168	1
auto[TlIntgErrBoth]	partial	auto[0]	44	1			T107	1		T108	1		T109	1
auto[TlIntgErrBoth]	partial	auto[1]	58	1			T108	2		T109	5		T169	1
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T168	1		T170	2		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T107	1		T171	1		T170	1