Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	44282	0	0
entropy_period_rd_A	2147483647	2596	0	0
intr_enable_rd_A	2147483647	3573	0	0
prefix_0_rd_A	2147483647	2642	0	0
prefix_10_rd_A	2147483647	2591	0	0
prefix_1_rd_A	2147483647	2754	0	0
prefix_2_rd_A	2147483647	2657	0	0
prefix_3_rd_A	2147483647	2535	0	0
prefix_4_rd_A	2147483647	2765	0	0
prefix_5_rd_A	2147483647	2763	0	0
prefix_6_rd_A	2147483647	2621	0	0
prefix_7_rd_A	2147483647	2535	0	0
prefix_8_rd_A	2147483647	2605	0	0
prefix_9_rd_A	2147483647	2789	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	44282	0	0
T29	162601	25565	0	0
T47	0	15047	0	0
T48	0	1	0	0
T106	0	60	0	0
T114	0	192	0	0
T115	0	175	0	0
T116	0	1	0	0
T119	0	2	0	0
T120	0	1	0	0
T121	111543	0	0	0
T122	242623	0	0	0
T123	64723	0	0	0
T124	6204	0	0	0
T125	29012	0	0	0
T126	1313	0	0	0
T127	433508	0	0	0
T128	1730	0	0	0
T129	7401	0	0	0
T130	0	2	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2596	0	0
T93	16774	76	0	0
T100	7243	12	0	0
T101	11654	48	0	0
T103	5233	20	0	0
T104	6115	20	0	0
T118	4869	11	0	0
T119	4253	8	0	0
T140	11794	68	0	0
T141	5558	43	0	0
T142	5677	36	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3573	0	0
T93	16774	129	0	0
T100	7243	9	0	0
T103	5233	10	0	0
T118	4869	2	0	0
T119	4253	9	0	0
T140	11794	103	0	0
T141	5558	33	0	0
T143	793	7	0	0
T144	1292	16	0	0
T145	1208	16	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2642	0	0
T93	16774	73	0	0
T100	7243	5	0	0
T101	11654	44	0	0
T103	5233	19	0	0
T104	6115	10	0	0
T118	4869	9	0	0
T119	4253	5	0	0
T140	11794	57	0	0
T141	5558	2	0	0
T142	5677	11	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2591	0	0
T93	16774	79	0	0
T100	7243	8	0	0
T101	11654	5	0	0
T103	5233	12	0	0
T114	12971	10	0	0
T118	4869	10	0	0
T119	4253	9	0	0
T140	11794	58	0	0
T141	5558	3	0	0
T142	5677	7	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2754	0	0
T93	16774	69	0	0
T100	7243	10	0	0
T101	11654	25	0	0
T103	5233	25	0	0
T114	12971	3	0	0
T118	4869	4	0	0
T119	4253	5	0	0
T140	11794	63	0	0
T141	5558	55	0	0
T142	5677	61	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2657	0	0
T93	16774	59	0	0
T100	7243	6	0	0
T101	11654	36	0	0
T103	5233	21	0	0
T104	6115	15	0	0
T118	4869	3	0	0
T140	11794	52	0	0
T141	5558	20	0	0
T142	5677	12	0	0
T146	12604	70	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2535	0	0
T93	16774	45	0	0
T100	7243	4	0	0
T101	11654	36	0	0
T103	5233	6	0	0
T114	12971	8	0	0
T118	4869	12	0	0
T119	4253	7	0	0
T140	11794	63	0	0
T141	5558	38	0	0
T142	5677	5	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2765	0	0
T93	16774	73	0	0
T100	7243	13	0	0
T101	11654	56	0	0
T103	5233	25	0	0
T104	6115	18	0	0
T118	4869	16	0	0
T119	4253	9	0	0
T140	11794	45	0	0
T141	5558	6	0	0
T142	5677	56	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2763	0	0
T93	16774	67	0	0
T100	7243	2	0	0
T101	11654	33	0	0
T103	5233	18	0	0
T104	6115	14	0	0
T118	4869	3	0	0
T119	4253	8	0	0
T140	11794	34	0	0
T141	5558	24	0	0
T142	5677	21	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2621	0	0
T93	16774	53	0	0
T100	7243	10	0	0
T101	11654	16	0	0
T103	5233	8	0	0
T104	6115	14	0	0
T118	4869	9	0	0
T119	4253	14	0	0
T140	11794	74	0	0
T141	5558	33	0	0
T142	5677	7	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2535	0	0
T93	16774	35	0	0
T100	7243	11	0	0
T101	11654	38	0	0
T103	5233	29	0	0
T104	6115	21	0	0
T118	4869	12	0	0
T119	4253	6	0	0
T140	11794	57	0	0
T141	5558	33	0	0
T142	5677	16	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2605	0	0
T93	16774	55	0	0
T100	7243	11	0	0
T101	11654	39	0	0
T103	5233	12	0	0
T104	6115	17	0	0
T118	4869	10	0	0
T119	4253	10	0	0
T140	11794	59	0	0
T141	5558	23	0	0
T142	5677	22	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2789	0	0
T93	16774	66	0	0
T100	7243	9	0	0
T101	11654	42	0	0
T103	5233	31	0	0
T104	6115	18	0	0
T118	4869	8	0	0
T119	4253	3	0	0
T140	11794	47	0	0
T141	5558	23	0	0
T142	5677	33	0	0