Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
337380 |
1 |
|
|
T1 |
166 |
|
T3 |
501 |
|
T18 |
467 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
177309 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
118029 |
1 |
|
|
T1 |
164 |
|
T3 |
495 |
|
T18 |
15 |
seven_bytes |
6030 |
1 |
|
|
T18 |
10 |
|
T24 |
26 |
|
T41 |
112 |
six_bytes |
5967 |
1 |
|
|
T18 |
11 |
|
T24 |
22 |
|
T41 |
109 |
five_bytes |
6017 |
1 |
|
|
T18 |
17 |
|
T24 |
25 |
|
T41 |
122 |
four_bytes |
5977 |
1 |
|
|
T18 |
11 |
|
T24 |
22 |
|
T41 |
106 |
three_bytes |
6082 |
1 |
|
|
T18 |
12 |
|
T24 |
30 |
|
T41 |
116 |
two_bytes |
5974 |
1 |
|
|
T18 |
7 |
|
T24 |
26 |
|
T41 |
122 |
one_byte |
5995 |
1 |
|
|
T18 |
14 |
|
T24 |
27 |
|
T41 |
140 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
330912 |
1 |
|
|
T1 |
162 |
|
T3 |
489 |
|
T18 |
459 |
auto[1] |
6468 |
1 |
|
|
T1 |
4 |
|
T3 |
12 |
|
T18 |
8 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
337380 |
1 |
|
|
T1 |
166 |
|
T3 |
501 |
|
T18 |
467 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
337356 |
1 |
|
|
T1 |
166 |
|
T3 |
501 |
|
T18 |
467 |
auto[1] |
24 |
1 |
|
|
T25 |
1 |
|
T38 |
1 |
|
T40 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
2224 |
1 |
|
|
T1 |
2 |
|
T3 |
6 |
|
T25 |
60 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
6468 |
1 |
|
|
T1 |
4 |
|
T3 |
12 |
|
T18 |
8 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
167929 |
1 |
|
|
T1 |
2 |
|
T3 |
206 |
|
T18 |
130 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
87827 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
59362 |
1 |
|
|
T1 |
1 |
|
T3 |
203 |
|
T18 |
4 |
seven_bytes |
3055 |
1 |
|
|
T18 |
2 |
|
T24 |
21 |
|
T41 |
33 |
six_bytes |
2908 |
1 |
|
|
T18 |
2 |
|
T24 |
25 |
|
T41 |
48 |
five_bytes |
2998 |
1 |
|
|
T18 |
4 |
|
T24 |
25 |
|
T41 |
44 |
four_bytes |
3000 |
1 |
|
|
T18 |
4 |
|
T24 |
29 |
|
T41 |
39 |
three_bytes |
3009 |
1 |
|
|
T18 |
2 |
|
T24 |
19 |
|
T41 |
47 |
two_bytes |
2936 |
1 |
|
|
T18 |
3 |
|
T24 |
25 |
|
T41 |
35 |
one_byte |
2834 |
1 |
|
|
T18 |
2 |
|
T24 |
23 |
|
T41 |
30 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
164792 |
1 |
|
|
T3 |
200 |
|
T18 |
128 |
|
T25 |
2407 |
auto[1] |
3137 |
1 |
|
|
T1 |
2 |
|
T3 |
6 |
|
T18 |
2 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
167929 |
1 |
|
|
T1 |
2 |
|
T3 |
206 |
|
T18 |
130 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
167916 |
1 |
|
|
T1 |
1 |
|
T3 |
206 |
|
T18 |
130 |
auto[1] |
13 |
1 |
|
|
T1 |
1 |
|
T163 |
2 |
|
T164 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1101 |
1 |
|
|
T1 |
1 |
|
T3 |
3 |
|
T25 |
34 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3137 |
1 |
|
|
T1 |
2 |
|
T3 |
6 |
|
T18 |
2 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
164058 |
1 |
|
|
T1 |
74 |
|
T3 |
327 |
|
T18 |
188 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
87018 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
56598 |
1 |
|
|
T1 |
73 |
|
T3 |
322 |
|
T18 |
9 |
seven_bytes |
2901 |
1 |
|
|
T18 |
5 |
|
T24 |
17 |
|
T41 |
22 |
six_bytes |
2936 |
1 |
|
|
T18 |
7 |
|
T24 |
15 |
|
T41 |
22 |
five_bytes |
2923 |
1 |
|
|
T18 |
2 |
|
T24 |
17 |
|
T41 |
28 |
four_bytes |
2954 |
1 |
|
|
T18 |
7 |
|
T24 |
17 |
|
T41 |
14 |
three_bytes |
2922 |
1 |
|
|
T18 |
5 |
|
T24 |
16 |
|
T41 |
25 |
two_bytes |
2888 |
1 |
|
|
T18 |
2 |
|
T24 |
11 |
|
T41 |
18 |
one_byte |
2918 |
1 |
|
|
T18 |
10 |
|
T24 |
23 |
|
T41 |
36 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
160914 |
1 |
|
|
T1 |
72 |
|
T3 |
317 |
|
T18 |
186 |
auto[1] |
3144 |
1 |
|
|
T1 |
2 |
|
T3 |
10 |
|
T18 |
2 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
164058 |
1 |
|
|
T1 |
74 |
|
T3 |
327 |
|
T18 |
188 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
164045 |
1 |
|
|
T1 |
74 |
|
T3 |
327 |
|
T18 |
188 |
auto[1] |
13 |
1 |
|
|
T38 |
2 |
|
T104 |
1 |
|
T165 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1056 |
1 |
|
|
T1 |
1 |
|
T3 |
5 |
|
T25 |
36 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3144 |
1 |
|
|
T1 |
2 |
|
T3 |
10 |
|
T18 |
2 |