Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

253692354

1

T1

3967

T2

673

T3

60599

full_word

198536432

1

T1

7970

T2

1429

T3

218216

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	452228496	1			T1	11937		T2	2102		T3	278815
auto[TlIntgErrCmd]	93	1			T109	8		T110	2		T111	5
auto[TlIntgErrData]	113	1			T109	5		T110	5		T111	7
auto[TlIntgErrBoth]	84	1			T109	7		T110	3		T111	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

238822389

1

T1

8486

T2

1095

T3

122515

auto[1]

213406397

1

T1

3451

T2

1007

T3

156300

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	152009630	1			T1	2703		T2	403		T3	46947
auto[TlIntgErrNone]	partial	auto[1]	101682451	1			T1	1264		T2	270		T3	13652
auto[TlIntgErrNone]	full_word	auto[0]	86812626	1			T1	5783		T2	692		T3	75568
auto[TlIntgErrNone]	full_word	auto[1]	111723789	1			T1	2187		T2	737		T3	142648
auto[TlIntgErrCmd]	partial	auto[0]	32	1			T109	2		T111	3		T129	4
auto[TlIntgErrCmd]	partial	auto[1]	54	1			T109	5		T110	2		T111	1
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T109	1		T111	1		T129	1
auto[TlIntgErrCmd]	full_word	auto[1]	2	1			T179	1		T180	1		-	-
auto[TlIntgErrData]	partial	auto[0]	51	1			T109	3		T110	2		T111	4
auto[TlIntgErrData]	partial	auto[1]	56	1			T109	2		T110	3		T111	3
auto[TlIntgErrData]	full_word	auto[0]	2	1			T181	1		T182	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	4	1			T129	1		T177	1		T115	1
auto[TlIntgErrBoth]	partial	auto[0]	41	1			T109	3		T110	2		T111	5
auto[TlIntgErrBoth]	partial	auto[1]	39	1			T109	4		T110	1		T111	3
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T177	1		T183	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	2	1			T129	1		T182	1		-	-