Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	96.27	93.33	100.00	92.31	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	96603	0	0
entropy_period_rd_A	2147483647	1306	0	0
intr_enable_rd_A	2147483647	1877	0	0
prefix_0_rd_A	2147483647	1196	0	0
prefix_10_rd_A	2147483647	1186	0	0
prefix_1_rd_A	2147483647	1163	0	0
prefix_2_rd_A	2147483647	1169	0	0
prefix_3_rd_A	2147483647	1159	0	0
prefix_4_rd_A	2147483647	1149	0	0
prefix_5_rd_A	2147483647	1150	0	0
prefix_6_rd_A	2147483647	1180	0	0
prefix_7_rd_A	2147483647	1246	0	0
prefix_8_rd_A	2147483647	1130	0	0
prefix_9_rd_A	2147483647	1252	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	96603	0	0
T32	242366	34909	0	0
T53	0	35299	0	0
T54	0	23174	0	0
T110	0	2	0	0
T111	0	2	0	0
T116	0	1	0	0
T118	0	164	0	0
T119	0	11	0	0
T120	479558	0	0	0
T121	227704	0	0	0
T122	225594	0	0	0
T123	4230	0	0	0
T124	195384	0	0	0
T125	50374	0	0	0
T126	30984	0	0	0
T127	17522	0	0	0
T128	6121	0	0	0
T129	0	1	0	0
T130	0	6	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1306	0	0
T92	5858	28	0	0
T93	6452	42	0	0
T109	22638	146	0	0
T117	4314	6	0	0
T143	8301	14	0	0
T144	2072	5	0	0
T145	2715	10	0	0
T146	12414	54	0	0
T147	10732	6	0	0
T148	5551	16	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1877	0	0
T92	5858	28	0	0
T93	6452	50	0	0
T109	22638	147	0	0
T113	1561	25	0	0
T117	4314	6	0	0
T143	8301	25	0	0
T144	2072	4	0	0
T149	1232	22	0	0
T150	993	14	0	0
T151	1578	35	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1196	0	0
T92	5858	18	0	0
T93	6452	21	0	0
T109	22638	95	0	0
T117	4314	6	0	0
T143	8301	16	0	0
T145	2715	2	0	0
T146	12414	41	0	0
T148	5551	32	0	0
T152	12317	77	0	0
T153	3777	15	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1186	0	0
T92	5858	14	0	0
T93	6452	33	0	0
T109	22638	89	0	0
T117	4314	9	0	0
T143	8301	23	0	0
T144	2072	1	0	0
T145	2715	2	0	0
T146	12414	35	0	0
T148	5551	23	0	0
T152	12317	59	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1163	0	0
T92	5858	14	0	0
T93	6452	22	0	0
T109	22638	107	0	0
T143	8301	17	0	0
T145	2715	8	0	0
T146	12414	37	0	0
T148	5551	12	0	0
T152	12317	85	0	0
T153	3777	15	0	0
T154	7401	13	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1169	0	0
T92	5858	7	0	0
T93	6452	33	0	0
T109	22638	63	0	0
T117	4314	4	0	0
T143	8301	12	0	0
T144	2072	9	0	0
T145	2715	16	0	0
T146	12414	37	0	0
T148	5551	32	0	0
T152	12317	63	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1159	0	0
T92	5858	15	0	0
T93	6452	16	0	0
T109	22638	50	0	0
T143	8301	18	0	0
T144	2072	3	0	0
T145	2715	4	0	0
T146	12414	49	0	0
T148	5551	18	0	0
T152	12317	59	0	0
T153	3777	9	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1149	0	0
T92	5858	18	0	0
T93	6452	28	0	0
T109	22638	72	0	0
T117	4314	6	0	0
T143	8301	23	0	0
T144	2072	6	0	0
T145	2715	8	0	0
T146	12414	44	0	0
T147	10732	6	0	0
T148	5551	7	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1150	0	0
T92	5858	16	0	0
T93	6452	33	0	0
T109	22638	71	0	0
T117	4314	7	0	0
T143	8301	12	0	0
T144	2072	2	0	0
T145	2715	1	0	0
T146	12414	36	0	0
T148	5551	21	0	0
T155	14647	3	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1180	0	0
T92	5858	23	0	0
T93	6452	29	0	0
T109	22638	84	0	0
T117	4314	2	0	0
T143	8301	12	0	0
T144	2072	7	0	0
T145	2715	6	0	0
T146	12414	34	0	0
T148	5551	13	0	0
T152	12317	86	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1246	0	0
T92	5858	27	0	0
T93	6452	13	0	0
T109	22638	85	0	0
T117	4314	4	0	0
T143	8301	20	0	0
T144	2072	1	0	0
T145	2715	9	0	0
T146	12414	52	0	0
T148	5551	34	0	0
T152	12317	75	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1130	0	0
T92	5858	17	0	0
T93	6452	45	0	0
T109	22638	79	0	0
T143	8301	13	0	0
T144	2072	3	0	0
T145	2715	8	0	0
T146	12414	30	0	0
T148	5551	19	0	0
T152	12317	57	0	0
T153	3777	7	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1252	0	0
T92	5858	20	0	0
T93	6452	40	0	0
T109	22638	90	0	0
T117	4314	7	0	0
T143	8301	18	0	0
T144	2072	4	0	0
T145	2715	4	0	0
T146	12414	39	0	0
T148	5551	25	0	0
T152	12317	70	0	0