Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

254898724

1

T1

716832

T2

393549

T3

2803

full_word

200570201

1

T1

503813

T2

261223

T3

5812

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	455468605	1			T1	122064		T2	654772		T3	8615
auto[TlIntgErrCmd]	114	1			T55	7		T111	8		T112	6
auto[TlIntgErrData]	98	1			T55	7		T111	7		T112	10
auto[TlIntgErrBoth]	108	1			T55	6		T111	5		T112	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

240086336

1

T1

646147

T2

335663

T3

6023

auto[1]

215382589

1

T1

574498

T2

319109

T3

2592

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	152869939	1			T1	432715		T2	237583		T3	1711
auto[TlIntgErrNone]	partial	auto[1]	102028489	1			T1	284117		T2	155966		T3	1092
auto[TlIntgErrNone]	full_word	auto[0]	87216252	1			T1	213432		T2	98080		T3	4312
auto[TlIntgErrNone]	full_word	auto[1]	113353925	1			T1	290381		T2	163143		T3	1500
auto[TlIntgErrCmd]	partial	auto[0]	48	1			T55	3		T111	5		T112	4
auto[TlIntgErrCmd]	partial	auto[1]	60	1			T55	4		T111	3		T112	1
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T175	1		T176	1		T177	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T112	1		T178	1		T179	1
auto[TlIntgErrData]	partial	auto[0]	44	1			T55	4		T111	2		T112	6
auto[TlIntgErrData]	partial	auto[1]	44	1			T55	3		T111	4		T112	3
auto[TlIntgErrData]	full_word	auto[0]	5	1			T136	1		T174	1		T178	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T111	1		T112	1		T135	1
auto[TlIntgErrBoth]	partial	auto[0]	43	1			T55	2		T111	2		T112	1
auto[TlIntgErrBoth]	partial	auto[1]	57	1			T55	4		T111	3		T112	3
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T175	1		T180	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T135	1		T178	2		T181	1