Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	96.27	93.33	100.00	92.31	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	51138	0	0
entropy_period_rd_A	2147483647	1698	0	0
intr_enable_rd_A	2147483647	2324	0	0
prefix_0_rd_A	2147483647	1648	0	0
prefix_10_rd_A	2147483647	1481	0	0
prefix_1_rd_A	2147483647	1563	0	0
prefix_2_rd_A	2147483647	1665	0	0
prefix_3_rd_A	2147483647	1445	0	0
prefix_4_rd_A	2147483647	1503	0	0
prefix_5_rd_A	2147483647	1542	0	0
prefix_6_rd_A	2147483647	1454	0	0
prefix_7_rd_A	2147483647	1594	0	0
prefix_8_rd_A	2147483647	1632	0	0
prefix_9_rd_A	2147483647	1553	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	51138	0	0
T53	253176	19427	0	0
T54	0	28319	0	0
T55	0	4	0	0
T109	0	91	0	0
T111	0	4	0	0
T112	0	2	0	0
T113	0	141	0	0
T114	0	121	0	0
T123	0	120	0	0
T124	0	2	0	0
T126	951546	0	0	0
T127	20351	0	0	0
T128	1452	0	0	0
T129	798256	0	0	0
T130	502845	0	0	0
T131	930088	0	0	0
T132	135486	0	0	0
T133	455009	0	0	0
T134	1579	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1698	0	0
T53	253176	56	0	0
T95	0	217	0	0
T103	0	8	0	0
T110	0	31	0	0
T111	0	119	0	0
T124	0	2	0	0
T126	951546	0	0	0
T127	20351	0	0	0
T128	1452	0	0	0
T129	798256	0	0	0
T130	502845	0	0	0
T131	930088	0	0	0
T132	135486	0	0	0
T133	455009	0	0	0
T134	1579	0	0	0
T135	0	83	0	0
T136	0	50	0	0
T147	0	26	0	0
T148	0	15	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2324	0	0
T53	253176	65	0	0
T95	0	195	0	0
T103	0	9	0	0
T110	0	58	0	0
T111	0	186	0	0
T124	0	5	0	0
T126	951546	0	0	0
T127	20351	0	0	0
T128	1452	0	0	0
T129	798256	0	0	0
T130	502845	0	0	0
T131	930088	0	0	0
T132	135486	0	0	0
T133	455009	0	0	0
T134	1579	0	0	0
T136	0	55	0	0
T147	0	45	0	0
T148	0	35	0	0
T149	0	15	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1648	0	0
T53	253176	53	0	0
T95	0	227	0	0
T103	0	14	0	0
T104	0	63	0	0
T110	0	25	0	0
T111	0	86	0	0
T126	951546	0	0	0
T127	20351	0	0	0
T128	1452	0	0	0
T129	798256	0	0	0
T130	502845	0	0	0
T131	930088	0	0	0
T132	135486	0	0	0
T133	455009	0	0	0
T134	1579	0	0	0
T135	0	80	0	0
T136	0	42	0	0
T147	0	114	0	0
T148	0	53	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1481	0	0
T53	253176	58	0	0
T95	0	231	0	0
T103	0	19	0	0
T110	0	39	0	0
T111	0	82	0	0
T124	0	7	0	0
T126	951546	0	0	0
T127	20351	0	0	0
T128	1452	0	0	0
T129	798256	0	0	0
T130	502845	0	0	0
T131	930088	0	0	0
T132	135486	0	0	0
T133	455009	0	0	0
T134	1579	0	0	0
T135	0	82	0	0
T136	0	39	0	0
T147	0	23	0	0
T148	0	48	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1563	0	0
T53	253176	40	0	0
T95	0	215	0	0
T103	0	5	0	0
T110	0	31	0	0
T111	0	96	0	0
T124	0	3	0	0
T126	951546	0	0	0
T127	20351	0	0	0
T128	1452	0	0	0
T129	798256	0	0	0
T130	502845	0	0	0
T131	930088	0	0	0
T132	135486	0	0	0
T133	455009	0	0	0
T134	1579	0	0	0
T135	0	112	0	0
T136	0	26	0	0
T147	0	42	0	0
T148	0	71	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1665	0	0
T53	253176	64	0	0
T95	0	238	0	0
T103	0	6	0	0
T104	0	50	0	0
T110	0	32	0	0
T111	0	79	0	0
T126	951546	0	0	0
T127	20351	0	0	0
T128	1452	0	0	0
T129	798256	0	0	0
T130	502845	0	0	0
T131	930088	0	0	0
T132	135486	0	0	0
T133	455009	0	0	0
T134	1579	0	0	0
T135	0	82	0	0
T136	0	48	0	0
T147	0	51	0	0
T148	0	54	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1445	0	0
T53	253176	60	0	0
T95	0	230	0	0
T103	0	9	0	0
T110	0	26	0	0
T111	0	71	0	0
T124	0	3	0	0
T126	951546	0	0	0
T127	20351	0	0	0
T128	1452	0	0	0
T129	798256	0	0	0
T130	502845	0	0	0
T131	930088	0	0	0
T132	135486	0	0	0
T133	455009	0	0	0
T134	1579	0	0	0
T135	0	55	0	0
T136	0	42	0	0
T147	0	83	0	0
T148	0	28	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1503	0	0
T53	253176	59	0	0
T95	0	183	0	0
T103	0	10	0	0
T110	0	22	0	0
T111	0	72	0	0
T113	0	12	0	0
T114	0	4	0	0
T126	951546	0	0	0
T127	20351	0	0	0
T128	1452	0	0	0
T129	798256	0	0	0
T130	502845	0	0	0
T131	930088	0	0	0
T132	135486	0	0	0
T133	455009	0	0	0
T134	1579	0	0	0
T136	0	49	0	0
T147	0	73	0	0
T148	0	66	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1542	0	0
T53	253176	59	0	0
T95	0	188	0	0
T103	0	3	0	0
T110	0	44	0	0
T111	0	69	0	0
T113	0	9	0	0
T126	951546	0	0	0
T127	20351	0	0	0
T128	1452	0	0	0
T129	798256	0	0	0
T130	502845	0	0	0
T131	930088	0	0	0
T132	135486	0	0	0
T133	455009	0	0	0
T134	1579	0	0	0
T135	0	62	0	0
T136	0	69	0	0
T147	0	41	0	0
T148	0	23	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1454	0	0
T53	253176	31	0	0
T95	0	216	0	0
T103	0	4	0	0
T104	0	67	0	0
T110	0	36	0	0
T111	0	78	0	0
T126	951546	0	0	0
T127	20351	0	0	0
T128	1452	0	0	0
T129	798256	0	0	0
T130	502845	0	0	0
T131	930088	0	0	0
T132	135486	0	0	0
T133	455009	0	0	0
T134	1579	0	0	0
T135	0	58	0	0
T136	0	53	0	0
T147	0	27	0	0
T148	0	34	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1594	0	0
T53	253176	77	0	0
T95	0	216	0	0
T103	0	10	0	0
T110	0	41	0	0
T111	0	81	0	0
T114	0	4	0	0
T124	0	5	0	0
T126	951546	0	0	0
T127	20351	0	0	0
T128	1452	0	0	0
T129	798256	0	0	0
T130	502845	0	0	0
T131	930088	0	0	0
T132	135486	0	0	0
T133	455009	0	0	0
T134	1579	0	0	0
T136	0	47	0	0
T147	0	47	0	0
T148	0	13	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1632	0	0
T53	253176	51	0	0
T95	0	217	0	0
T103	0	6	0	0
T110	0	22	0	0
T111	0	86	0	0
T124	0	8	0	0
T126	951546	0	0	0
T127	20351	0	0	0
T128	1452	0	0	0
T129	798256	0	0	0
T130	502845	0	0	0
T131	930088	0	0	0
T132	135486	0	0	0
T133	455009	0	0	0
T134	1579	0	0	0
T135	0	91	0	0
T136	0	33	0	0
T147	0	76	0	0
T148	0	63	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1553	0	0
T53	253176	79	0	0
T95	0	214	0	0
T103	0	6	0	0
T110	0	33	0	0
T111	0	88	0	0
T124	0	5	0	0
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T127	20351	0	0	0
T128	1452	0	0	0
T129	798256	0	0	0
T130	502845	0	0	0
T131	930088	0	0	0
T132	135486	0	0	0
T133	455009	0	0	0
T134	1579	0	0	0
T135	0	95	0	0
T136	0	40	0	0
T147	0	72	0	0
T148	0	66	0	0