Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	253717417	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

199468715

1

T1

879

T2

261257

T3

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	239172133	1			T1	494		T2	342461		T3	1
values[0x0]	102854118	1			T1	438		T2	156165		T3	1
values[0x1]	111159881	1			T1	459		T2	169749		T3	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	197823585	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

255362547

1

T1

1065

T2

350801

T3

2

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1343940	1			T2	2557		T4	473		T14	3605
valid_sources[0x01]	1350247	1			T2	2534		T4	463		T14	3648
valid_sources[0x02]	1351308	1			T2	2581		T4	452		T14	3680
valid_sources[0x03]	1354858	1			T2	2589		T4	464		T14	3577
valid_sources[0x04]	1383821	1			T2	2619		T4	449		T14	3644
valid_sources[0x05]	1349855	1			T2	2625		T4	446		T14	3626
valid_sources[0x06]	2444940	1			T2	2699		T4	473		T14	3482
valid_sources[0x07]	1348087	1			T2	2560		T4	434		T14	3571
valid_sources[0x08]	1618432	1			T2	2747		T4	427		T14	3584
valid_sources[0x09]	1350866	1			T2	2601		T4	495		T14	3613
valid_sources[0x0a]	2301094	1			T2	2582		T4	476		T14	3683
valid_sources[0x0b]	3158466	1			T2	2520		T4	439		T14	3554
valid_sources[0x0c]	1353150	1			T2	2553		T4	503		T14	3505
valid_sources[0x0d]	1349314	1			T2	2617		T4	476		T14	3524
valid_sources[0x0e]	1564298	1			T2	2625		T4	475		T14	3564
valid_sources[0x0f]	1494706	1			T2	2620		T4	464		T14	3575
valid_sources[0x10]	1349059	1			T2	2527		T4	478		T14	3557
valid_sources[0x11]	1357500	1			T2	2701		T4	458		T14	3626
valid_sources[0x12]	1495930	1			T2	2597		T4	436		T14	3645
valid_sources[0x13]	1347127	1			T2	2661		T4	477		T14	3681
valid_sources[0x14]	1416675	1			T2	2616		T4	486		T14	3555
valid_sources[0x15]	1351572	1			T2	2571		T4	429		T14	3610
valid_sources[0x16]	1507917	1			T2	2620		T4	421		T14	3612
valid_sources[0x17]	1481203	1			T2	2648		T4	452		T14	3659
valid_sources[0x18]	6192902	1			T2	2616		T4	433		T14	3659
valid_sources[0x19]	1354164	1			T2	2738		T4	485		T14	3577
valid_sources[0x1a]	1349289	1			T2	2677		T4	470		T14	3592
valid_sources[0x1b]	1345218	1			T2	2575		T4	453		T14	3517
valid_sources[0x1c]	1348230	1			T2	2690		T4	500		T14	3622
valid_sources[0x1d]	2195465	1			T2	2577		T4	464		T14	3781
valid_sources[0x1e]	3408986	1			T2	2668		T4	480		T14	3628
valid_sources[0x1f]	1348098	1			T2	2557		T4	432		T14	3575
valid_sources[0x20]	1343007	1			T2	2712		T4	444		T14	3669
valid_sources[0x21]	1464944	1			T2	2698		T4	431		T14	3525
valid_sources[0x22]	2014789	1			T2	2656		T4	513		T14	3538
valid_sources[0x23]	3859898	1			T2	2735		T4	460		T14	3567
valid_sources[0x24]	1675912	1			T2	2683		T4	484		T14	3590
valid_sources[0x25]	1936000	1			T2	2549		T4	450		T14	3652
valid_sources[0x26]	1382774	1			T2	2586		T4	476		T14	3599
valid_sources[0x27]	1347529	1			T2	2644		T4	469		T14	3636
valid_sources[0x28]	2277918	1			T2	2640		T4	446		T14	3458
valid_sources[0x29]	2282289	1			T2	2555		T4	479		T14	3487
valid_sources[0x2a]	1344128	1			T2	2584		T4	454		T14	3636
valid_sources[0x2b]	1347512	1			T2	2649		T4	476		T14	3695
valid_sources[0x2c]	1347115	1			T2	2590		T4	427		T14	3667
valid_sources[0x2d]	3406249	1			T2	2603		T4	473		T14	3730
valid_sources[0x2e]	1573730	1			T2	2570		T4	501		T14	3452
valid_sources[0x2f]	1347277	1			T2	2591		T4	469		T14	3533
valid_sources[0x30]	2006381	1			T2	2685		T4	446		T14	3651
valid_sources[0x31]	1347112	1			T2	2615		T4	483		T14	3490
valid_sources[0x32]	1836793	1			T2	2612		T4	473		T14	3531
valid_sources[0x33]	1349366	1			T2	2586		T4	503		T14	3573
valid_sources[0x34]	1345974	1			T2	2688		T4	470		T14	3652
valid_sources[0x35]	1502541	1			T2	2582		T4	454		T14	3700
valid_sources[0x36]	1382370	1			T2	2516		T4	455		T14	3521
valid_sources[0x37]	1345219	1			T2	2662		T4	450		T14	3632
valid_sources[0x38]	1345364	1			T2	2663		T4	475		T14	3659
valid_sources[0x39]	1361529	1			T2	2576		T4	485		T14	3579
valid_sources[0x3a]	1349829	1			T2	2689		T4	470		T14	3539
valid_sources[0x3b]	1339604	1			T2	2631		T4	443		T14	3692
valid_sources[0x3c]	2217151	1			T2	2588		T4	465		T14	3692
valid_sources[0x3d]	1349901	1			T2	2614		T4	448		T14	3567
valid_sources[0x3e]	1347275	1			T2	2580		T4	468		T14	3690
valid_sources[0x3f]	1345893	1			T2	2687		T4	438		T14	3595
valid_sources[0x40]	1343829	1			T2	2641		T4	436		T14	3586
valid_sources[0x41]	6370246	1			T2	2598		T4	459		T14	3613
valid_sources[0x42]	1342271	1			T2	2634		T4	462		T14	3682
valid_sources[0x43]	1341583	1			T2	2582		T4	447		T14	3580
valid_sources[0x44]	1341519	1			T2	2579		T4	437		T14	3516
valid_sources[0x45]	1350988	1			T2	2680		T4	450		T14	3577
valid_sources[0x46]	3382092	1			T2	2694		T4	440		T14	3735
valid_sources[0x47]	2165519	1			T2	2508		T4	465		T14	3538
valid_sources[0x48]	1348827	1			T2	2577		T4	488		T14	3658
valid_sources[0x49]	2015228	1			T2	2648		T4	542		T14	3602
valid_sources[0x4a]	1364021	1			T2	2597		T4	447		T14	3463
valid_sources[0x4b]	1756736	1			T2	2571		T4	480		T14	3580
valid_sources[0x4c]	1808637	1			T2	2502		T4	514		T14	3626
valid_sources[0x4d]	3554983	1			T2	2642		T4	446		T14	3624
valid_sources[0x4e]	2260390	1			T2	2611		T4	461		T14	3594
valid_sources[0x4f]	1802375	1			T2	2604		T4	446		T14	3587
valid_sources[0x50]	2059208	1			T2	2651		T4	489		T14	3584
valid_sources[0x51]	2258983	1			T2	2530		T4	502		T14	3635
valid_sources[0x52]	1426684	1			T2	2644		T4	452		T14	3621
valid_sources[0x53]	1350311	1			T2	2645		T4	436		T14	3595
valid_sources[0x54]	1346121	1			T2	2546		T4	466		T14	3616
valid_sources[0x55]	1340597	1			T2	2562		T4	471		T14	3576
valid_sources[0x56]	1352733	1			T2	2641		T4	459		T14	3508
valid_sources[0x57]	4141236	1			T2	2624		T4	453		T14	3658
valid_sources[0x58]	4012669	1			T2	2540		T4	467		T14	3596
valid_sources[0x59]	1349249	1			T2	2602		T4	459		T14	3577
valid_sources[0x5a]	7102648	1			T2	2676		T4	467		T14	3656
valid_sources[0x5b]	3740168	1			T2	2561		T4	461		T14	3521
valid_sources[0x5c]	1349823	1			T2	2600		T4	443		T14	3711
valid_sources[0x5d]	1347141	1			T2	2556		T4	510		T14	3558
valid_sources[0x5e]	1465701	1			T2	2654		T4	463		T14	3620
valid_sources[0x5f]	3764636	1			T2	2577		T4	505		T14	3496
valid_sources[0x60]	1436364	1			T2	2689		T4	444		T14	3658
valid_sources[0x61]	1348065	1			T2	2526		T4	416		T14	3597
valid_sources[0x62]	3774619	1			T2	2617		T4	444		T14	3682
valid_sources[0x63]	2384505	1			T2	2676		T4	494		T14	3577
valid_sources[0x64]	2287756	1			T2	2598		T4	474		T14	3599
valid_sources[0x65]	1346235	1			T2	2683		T4	511		T14	3654
valid_sources[0x66]	1344618	1			T2	2567		T4	470		T14	3501
valid_sources[0x67]	1340416	1			T2	2689		T4	476		T14	3428
valid_sources[0x68]	1344093	1			T2	2672		T4	474		T14	3676
valid_sources[0x69]	1341752	1			T2	2576		T4	501		T14	3643
valid_sources[0x6a]	1500317	1			T2	2542		T4	496		T14	3690
valid_sources[0x6b]	1344998	1			T2	2532		T4	431		T14	3683
valid_sources[0x6c]	1347506	1			T2	2665		T4	437		T14	3559
valid_sources[0x6d]	1339141	1			T2	2693		T4	478		T14	3538
valid_sources[0x6e]	1459519	1			T2	2614		T4	422		T14	3636
valid_sources[0x6f]	1354970	1			T2	2595		T4	474		T14	3609
valid_sources[0x70]	2011254	1			T2	2565		T4	487		T14	3709
valid_sources[0x71]	1786364	1			T2	2600		T4	487		T14	3546
valid_sources[0x72]	1353146	1			T2	2590		T4	493		T14	3528
valid_sources[0x73]	2246290	1			T2	2617		T4	471		T14	3503
valid_sources[0x74]	1349024	1			T2	2642		T4	452		T14	3519
valid_sources[0x75]	1344204	1			T2	2554		T4	462		T14	3580
valid_sources[0x76]	1343865	1			T2	2457		T4	454		T14	3638
valid_sources[0x77]	1340428	1			T2	2603		T4	426		T14	3689
valid_sources[0x78]	1342568	1			T2	2572		T4	469		T14	3546
valid_sources[0x79]	1349661	1			T2	2574		T4	436		T14	3626
valid_sources[0x7a]	1353476	1			T2	2650		T4	479		T14	3688
valid_sources[0x7b]	1342949	1			T2	2601		T4	427		T14	3568
valid_sources[0x7c]	1344337	1			T2	2640		T4	457		T14	3537
valid_sources[0x7d]	1349911	1			T2	2639		T4	467		T14	3590
valid_sources[0x7e]	5379038	1			T2	2683		T4	464		T14	3536
valid_sources[0x7f]	1493293	1			T2	2525		T4	466		T14	3694
valid_sources[0x80]	1383791	1			T2	2571		T4	489		T14	3359

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

86975491

1

T1

37

T2

100117

T3

1

values[0x0]

all_enables

biggest_size

60526062

1

T1

408

T2

87522

T4

10596

values[0x1]

all_enables

biggest_size

51967162

1

T1

434

T2

73618

T3

1