Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

254173036

1

T1

512

T2

407118

T3

1

full_word

199497671

1

T1

879

T2

261257

T3

2

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	453670437	1			T1	1391		T2	668375		T3	3
auto[TlIntgErrCmd]	99	1			T52	2		T119	7		T122	7
auto[TlIntgErrData]	88	1			T52	4		T119	1		T122	2
auto[TlIntgErrBoth]	83	1			T52	4		T119	2		T122	1

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

239261377

1

T1

494

T2

342461

T3

1

auto[1]

214409330

1

T1

897

T2

325914

T3

2

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	152278287	1			T1	457		T2	242344		T4	28163
auto[TlIntgErrNone]	partial	auto[1]	101894496	1			T1	55		T2	164774		T3	1
auto[TlIntgErrNone]	full_word	auto[0]	86982973	1			T1	37		T2	100117		T3	1
auto[TlIntgErrNone]	full_word	auto[1]	112514681	1			T1	842		T2	161140		T3	1
auto[TlIntgErrCmd]	partial	auto[0]	41	1			T119	5		T122	3		T189	2
auto[TlIntgErrCmd]	partial	auto[1]	51	1			T52	1		T119	2		T122	4
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T52	1		T192	1		T196	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T197	1		T198	1		T199	1
auto[TlIntgErrData]	partial	auto[0]	41	1			T52	2		T119	1		T189	1
auto[TlIntgErrData]	partial	auto[1]	43	1			T52	2		T122	1		T189	2
auto[TlIntgErrData]	full_word	auto[0]	2	1			T122	1		T200	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	2	1			T190	1		T196	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	26	1			T52	2		T119	1		T189	1
auto[TlIntgErrBoth]	partial	auto[1]	51	1			T52	2		T119	1		T122	1
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T190	1		T192	1		T198	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T189	1		T201	1		T199	1