Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	103783	0	0
entropy_period_rd_A	2147483647	1352	0	0
intr_enable_rd_A	2147483647	1797	0	0
prefix_0_rd_A	2147483647	1281	0	0
prefix_10_rd_A	2147483647	1177	0	0
prefix_1_rd_A	2147483647	1147	0	0
prefix_2_rd_A	2147483647	1325	0	0
prefix_3_rd_A	2147483647	1355	0	0
prefix_4_rd_A	2147483647	1258	0	0
prefix_5_rd_A	2147483647	1261	0	0
prefix_6_rd_A	2147483647	1273	0	0
prefix_7_rd_A	2147483647	1190	0	0
prefix_8_rd_A	2147483647	1262	0	0
prefix_9_rd_A	2147483647	1167	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	103783	0	0
T51	785639	100304	0	0
T53	0	15	0	0
T118	0	5	0	0
T119	0	1	0	0
T122	0	1	0	0
T123	0	252	0	0
T126	0	108	0	0
T130	0	162	0	0
T131	0	207	0	0
T135	0	5	0	0
T137	260692	0	0	0
T138	954835	0	0	0
T139	21969	0	0	0
T140	1809	0	0	0
T141	613733	0	0	0
T142	220629	0	0	0
T143	134512	0	0	0
T144	120689	0	0	0
T145	112936	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1352	0	0
T103	4458	12	0	0
T111	6532	21	0	0
T120	13154	80	0	0
T159	1653	16	0	0
T160	4325	14	0	0
T161	7449	11	0	0
T162	2417	6	0	0
T163	27145	206	0	0
T164	2347	2	0	0
T165	10688	48	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1797	0	0
T103	4458	11	0	0
T111	6532	28	0	0
T120	13154	97	0	0
T128	1569	9	0	0
T159	1653	1	0	0
T160	4325	14	0	0
T161	7449	36	0	0
T162	2417	8	0	0
T166	2169	1	0	0
T167	1822	13	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1281	0	0
T103	4458	26	0	0
T111	6532	30	0	0
T120	13154	69	0	0
T159	1653	2	0	0
T160	4325	5	0	0
T161	7449	10	0	0
T162	2417	1	0	0
T163	27145	211	0	0
T166	2169	3	0	0
T167	1822	9	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1177	0	0
T103	4458	8	0	0
T111	6532	36	0	0
T120	13154	64	0	0
T130	9032	4	0	0
T159	1653	5	0	0
T160	4325	12	0	0
T161	7449	12	0	0
T163	27145	178	0	0
T164	2347	2	0	0
T166	2169	4	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1147	0	0
T103	4458	25	0	0
T111	6532	29	0	0
T120	13154	43	0	0
T159	1653	1	0	0
T160	4325	1	0	0
T161	7449	14	0	0
T162	2417	9	0	0
T163	27145	222	0	0
T164	2347	4	0	0
T166	2169	6	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1325	0	0
T103	4458	18	0	0
T111	6532	28	0	0
T120	13154	59	0	0
T159	1653	2	0	0
T160	4325	5	0	0
T161	7449	23	0	0
T162	2417	17	0	0
T163	27145	223	0	0
T164	2347	2	0	0
T167	1822	6	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1355	0	0
T103	4458	20	0	0
T111	6532	26	0	0
T120	13154	70	0	0
T159	1653	3	0	0
T160	4325	1	0	0
T161	7449	13	0	0
T163	27145	204	0	0
T164	2347	2	0	0
T166	2169	1	0	0
T167	1822	3	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1258	0	0
T103	4458	9	0	0
T111	6532	23	0	0
T120	13154	55	0	0
T159	1653	4	0	0
T160	4325	12	0	0
T161	7449	16	0	0
T162	2417	11	0	0
T163	27145	211	0	0
T166	2169	1	0	0
T167	1822	5	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1261	0	0
T103	4458	18	0	0
T111	6532	28	0	0
T120	13154	50	0	0
T159	1653	3	0	0
T160	4325	5	0	0
T161	7449	25	0	0
T162	2417	2	0	0
T163	27145	215	0	0
T164	2347	2	0	0
T167	1822	6	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1273	0	0
T103	4458	17	0	0
T111	6532	32	0	0
T120	13154	65	0	0
T159	1653	7	0	0
T160	4325	12	0	0
T161	7449	19	0	0
T162	2417	5	0	0
T163	27145	224	0	0
T166	2169	6	0	0
T167	1822	6	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1190	0	0
T103	4458	16	0	0
T111	6532	41	0	0
T120	13154	60	0	0
T159	1653	6	0	0
T160	4325	9	0	0
T161	7449	27	0	0
T162	2417	3	0	0
T163	27145	191	0	0
T166	2169	3	0	0
T167	1822	7	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1262	0	0
T103	4458	20	0	0
T111	6532	34	0	0
T120	13154	57	0	0
T159	1653	3	0	0
T160	4325	9	0	0
T161	7449	11	0	0
T162	2417	3	0	0
T163	27145	219	0	0
T166	2169	7	0	0
T167	1822	5	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1167	0	0
T103	4458	19	0	0
T111	6532	26	0	0
T120	13154	63	0	0
T159	1653	4	0	0
T160	4325	11	0	0
T161	7449	12	0	0
T163	27145	176	0	0
T165	10688	42	0	0
T166	2169	2	0	0
T167	1822	8	0	0