Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	251649130	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

198299237

1

T1

339122

T2

261508

T3

100190

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	237446675	1			T1	445011		T2	337695		T3	125724
values[0x0]	102171623	1			T1	203470		T2	154054		T3	545241
values[0x1]	110330069	1			T1	223095		T2	167109		T3	588085

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	196243046	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

253705321

1

T1

456842

T2

348187

T3

130396

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1457442	1			T2	2732		T3	9382		T13	7
valid_sources[0x01]	2218364	1			T2	2535		T3	9326		T13	9
valid_sources[0x02]	3066879	1			T2	2529		T3	9321		T13	6
valid_sources[0x03]	2239407	1			T1	871576		T2	2597		T3	9424
valid_sources[0x04]	1412547	1			T2	2670		T3	9272		T13	10
valid_sources[0x05]	1369430	1			T2	2579		T3	9096		T13	8
valid_sources[0x06]	3352880	1			T2	2618		T3	9322		T13	9
valid_sources[0x07]	2019918	1			T2	2525		T3	9312		T13	3
valid_sources[0x08]	2520816	1			T2	2518		T3	9124		T13	11
valid_sources[0x09]	1367322	1			T2	2582		T3	9217		T13	12
valid_sources[0x0a]	1370552	1			T2	2522		T3	9294		T13	6
valid_sources[0x0b]	1372816	1			T2	2676		T3	9311		T13	8
valid_sources[0x0c]	1365241	1			T2	2595		T3	9198		T13	14
valid_sources[0x0d]	1365310	1			T2	2693		T3	9267		T13	7
valid_sources[0x0e]	3438479	1			T2	2489		T3	9430		T13	5
valid_sources[0x0f]	1441720	1			T2	2461		T3	9315		T13	10
valid_sources[0x10]	2247613	1			T2	2604		T3	9307		T13	10
valid_sources[0x11]	2233189	1			T2	2665		T3	9322		T13	13
valid_sources[0x12]	3090987	1			T2	2618		T3	9428		T13	6
valid_sources[0x13]	1363140	1			T2	2576		T3	9450		T13	8
valid_sources[0x14]	1652830	1			T2	2785		T3	9357		T13	8
valid_sources[0x15]	1834310	1			T2	2602		T3	9422		T13	3
valid_sources[0x16]	1367963	1			T2	2636		T3	9333		T13	13
valid_sources[0x17]	2228242	1			T2	2520		T3	9279		T13	10
valid_sources[0x18]	1492173	1			T2	2563		T3	9356		T13	12
valid_sources[0x19]	2617574	1			T2	2629		T3	9437		T13	5
valid_sources[0x1a]	1367793	1			T2	2603		T3	9251		T13	7
valid_sources[0x1b]	1836621	1			T2	2521		T3	9260		T13	8
valid_sources[0x1c]	1373949	1			T2	2554		T3	9366		T13	11
valid_sources[0x1d]	1504558	1			T2	2604		T3	9189		T13	7
valid_sources[0x1e]	1366693	1			T2	2529		T3	9317		T13	11
valid_sources[0x1f]	1366980	1			T2	2708		T3	9204		T13	14
valid_sources[0x20]	1382009	1			T2	2706		T3	9248		T13	10
valid_sources[0x21]	1363366	1			T2	2615		T3	9544		T13	10
valid_sources[0x22]	3419677	1			T2	2568		T3	9457		T13	13
valid_sources[0x23]	1371194	1			T2	2661		T3	9353		T13	11
valid_sources[0x24]	1865470	1			T2	2476		T3	9409		T13	5
valid_sources[0x25]	1360830	1			T2	2352		T3	9459		T13	10
valid_sources[0x26]	4785696	1			T2	2684		T3	9333		T13	12
valid_sources[0x27]	1364646	1			T2	2572		T3	9416		T13	8
valid_sources[0x28]	1834318	1			T2	2705		T3	9314		T13	6
valid_sources[0x29]	1367204	1			T2	2523		T3	9401		T13	10
valid_sources[0x2a]	2076613	1			T2	2653		T3	9421		T13	11
valid_sources[0x2b]	1359344	1			T2	2348		T3	9282		T13	13
valid_sources[0x2c]	1365249	1			T2	2615		T3	9331		T13	5
valid_sources[0x2d]	3415132	1			T2	2639		T3	9339		T13	11
valid_sources[0x2e]	1362077	1			T2	2546		T3	9364		T13	8
valid_sources[0x2f]	3408212	1			T2	2606		T3	9494		T13	9
valid_sources[0x30]	2235243	1			T2	2717		T3	9443		T13	13
valid_sources[0x31]	1371635	1			T2	2580		T3	9315		T13	7
valid_sources[0x32]	2337515	1			T2	2682		T3	9292		T13	9
valid_sources[0x33]	1470658	1			T2	2393		T3	9413		T13	11
valid_sources[0x34]	1466613	1			T2	2407		T3	9463		T13	10
valid_sources[0x35]	1374466	1			T2	2840		T3	9351		T13	12
valid_sources[0x36]	1364520	1			T2	2766		T3	9415		T13	9
valid_sources[0x37]	2300164	1			T2	2639		T3	9478		T13	11
valid_sources[0x38]	1383008	1			T2	2601		T3	9193		T13	6
valid_sources[0x39]	1369977	1			T2	2457		T3	9441		T13	8
valid_sources[0x3a]	1397452	1			T2	2635		T3	9341		T13	7
valid_sources[0x3b]	1376322	1			T2	2570		T3	9340		T13	9
valid_sources[0x3c]	1360492	1			T2	2714		T3	9447		T13	12
valid_sources[0x3d]	1369549	1			T2	2386		T3	9328		T13	13
valid_sources[0x3e]	1363964	1			T2	2681		T3	9325		T13	11
valid_sources[0x3f]	2107909	1			T2	2524		T3	9237		T13	9
valid_sources[0x40]	1369851	1			T2	2619		T3	9291		T13	8
valid_sources[0x41]	1361429	1			T2	2546		T3	9310		T13	10
valid_sources[0x42]	1375043	1			T2	2743		T3	9382		T13	5
valid_sources[0x43]	1426363	1			T2	2701		T3	9449		T13	9
valid_sources[0x44]	1366507	1			T2	2494		T3	9275		T13	8
valid_sources[0x45]	1378428	1			T2	2571		T3	9608		T13	11
valid_sources[0x46]	1367582	1			T2	2634		T3	9177		T13	14
valid_sources[0x47]	1361891	1			T2	2516		T3	9359		T13	16
valid_sources[0x48]	1509213	1			T2	2474		T3	9164		T13	11
valid_sources[0x49]	1776825	1			T2	2589		T3	9366		T13	9
valid_sources[0x4a]	1364972	1			T2	2493		T3	9124		T13	16
valid_sources[0x4b]	1582735	1			T2	2588		T3	9365		T13	7
valid_sources[0x4c]	1365693	1			T2	2447		T3	9277		T13	12
valid_sources[0x4d]	1381691	1			T2	2488		T3	9176		T13	9
valid_sources[0x4e]	2229331	1			T2	2318		T3	9288		T13	8
valid_sources[0x4f]	1371082	1			T2	2591		T3	9415		T13	13
valid_sources[0x50]	1381878	1			T2	2657		T3	9281		T13	2
valid_sources[0x51]	1505873	1			T2	2519		T3	9320		T13	8
valid_sources[0x52]	1369048	1			T2	2523		T3	9369		T13	7
valid_sources[0x53]	1363983	1			T2	2448		T3	9410		T13	14
valid_sources[0x54]	1482074	1			T2	2357		T3	9225		T13	10
valid_sources[0x55]	1462391	1			T2	2565		T3	9366		T13	9
valid_sources[0x56]	1378329	1			T2	2620		T3	9334		T13	11
valid_sources[0x57]	3379116	1			T2	2708		T3	9523		T13	7
valid_sources[0x58]	1361980	1			T2	2663		T3	9224		T13	9
valid_sources[0x59]	2551087	1			T2	2636		T3	9491		T13	14
valid_sources[0x5a]	1371046	1			T2	2506		T3	9407		T13	8
valid_sources[0x5b]	3750069	1			T2	2548		T3	9304		T13	11
valid_sources[0x5c]	1363319	1			T2	2663		T3	9315		T13	12
valid_sources[0x5d]	1370885	1			T2	2446		T3	9446		T13	5
valid_sources[0x5e]	2300744	1			T2	2529		T3	9374		T13	14
valid_sources[0x5f]	1890238	1			T2	2688		T3	9526		T13	15
valid_sources[0x60]	1368466	1			T2	2676		T3	9310		T13	5
valid_sources[0x61]	2037570	1			T2	2600		T3	9198		T13	8
valid_sources[0x62]	1442647	1			T2	2643		T3	9408		T13	10
valid_sources[0x63]	1370311	1			T2	2612		T3	9322		T13	11
valid_sources[0x64]	1369404	1			T2	2663		T3	9427		T13	7
valid_sources[0x65]	1369783	1			T2	2681		T3	9491		T13	17
valid_sources[0x66]	1362171	1			T2	2457		T3	9390		T13	14
valid_sources[0x67]	3441192	1			T2	2413		T3	9389		T13	15
valid_sources[0x68]	1365139	1			T2	2545		T3	9352		T13	4
valid_sources[0x69]	1833712	1			T2	2668		T3	9312		T13	3
valid_sources[0x6a]	1366287	1			T2	2606		T3	9236		T13	15
valid_sources[0x6b]	1377048	1			T2	2786		T3	9284		T13	3
valid_sources[0x6c]	1370669	1			T2	2550		T3	9220		T13	16
valid_sources[0x6d]	1361026	1			T2	2580		T3	9344		T13	4
valid_sources[0x6e]	1371468	1			T2	2619		T3	9311		T13	18
valid_sources[0x6f]	1478157	1			T2	2744		T3	9294		T13	9
valid_sources[0x70]	2069105	1			T2	2522		T3	9360		T13	6
valid_sources[0x71]	1359280	1			T2	2491		T3	9443		T13	13
valid_sources[0x72]	1371576	1			T2	2650		T3	9253		T13	8
valid_sources[0x73]	1484438	1			T2	2547		T3	9371		T13	6
valid_sources[0x74]	1367905	1			T2	2623		T3	9444		T13	10
valid_sources[0x75]	1361787	1			T2	2570		T3	9220		T13	10
valid_sources[0x76]	2099607	1			T2	2566		T3	9337		T13	9
valid_sources[0x77]	1370948	1			T2	2602		T3	9324		T13	1
valid_sources[0x78]	1363635	1			T2	2483		T3	9389		T13	9
valid_sources[0x79]	1374169	1			T2	2541		T3	9208		T13	10
valid_sources[0x7a]	1823323	1			T2	2620		T3	9462		T13	7
valid_sources[0x7b]	1366888	1			T2	2602		T3	9274		T13	10
valid_sources[0x7c]	1367910	1			T2	2466		T3	9286		T13	10
valid_sources[0x7d]	1367519	1			T2	2643		T3	9282		T13	9
valid_sources[0x7e]	1361868	1			T2	2782		T3	9360		T13	5
valid_sources[0x7f]	1370529	1			T2	2421		T3	9515		T13	7
valid_sources[0x80]	1369530	1			T2	2579		T3	9360		T13	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

86401950

1

T1

127993

T2

99100

T3

423059

values[0x0]

all_enables

biggest_size

60207086

1

T1

114295

T2

87928

T3

313069

values[0x1]

all_enables

biggest_size

51690201

1

T1

96834

T2

74480

T3

265777