Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

251859741

1

T1

532454

T2

397350

T3

138866

full_word

198312584

1

T1

339122

T2

261508

T3

100190

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	450172055	1			T1	871576		T2	658858		T3	239057
auto[TlIntgErrCmd]	86	1			T53	2		T114	8		T115	1
auto[TlIntgErrData]	91	1			T53	2		T114	8		T115	4
auto[TlIntgErrBoth]	93	1			T53	6		T114	4		T115	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

237488282

1

T1

445011

T2

337695

T3

125724

auto[1]

212684043

1

T1

426565

T2

321163

T3

113332

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	151082874	1			T1	317018		T2	238595		T3	834185
auto[TlIntgErrNone]	partial	auto[1]	100776609	1			T1	215436		T2	158755		T3	554480
auto[TlIntgErrNone]	full_word	auto[0]	86405290	1			T1	127993		T2	99100		T3	423059
auto[TlIntgErrNone]	full_word	auto[1]	111907282	1			T1	211129		T2	162408		T3	578846
auto[TlIntgErrCmd]	partial	auto[0]	38	1			T114	3		T115	1		T176	4
auto[TlIntgErrCmd]	partial	auto[1]	46	1			T53	2		T114	5		T176	2
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T183	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	1	1			T179	1		-	-		-	-
auto[TlIntgErrData]	partial	auto[0]	39	1			T53	1		T114	3		T115	1
auto[TlIntgErrData]	partial	auto[1]	49	1			T53	1		T114	4		T115	3
auto[TlIntgErrData]	full_word	auto[0]	1	1			T184	1		-	-		-	-
auto[TlIntgErrData]	full_word	auto[1]	2	1			T114	1		T176	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	36	1			T53	3		T114	3		T115	2
auto[TlIntgErrBoth]	partial	auto[1]	50	1			T53	3		T114	1		T115	2
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T176	1		T185	1		T186	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T115	1		T181	1		T187	1