Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	49833	0	0
entropy_period_rd_A	2147483647	1493	0	0
intr_enable_rd_A	2147483647	1962	0	0
prefix_0_rd_A	2147483647	1149	0	0
prefix_10_rd_A	2147483647	1196	0	0
prefix_1_rd_A	2147483647	1144	0	0
prefix_2_rd_A	2147483647	1194	0	0
prefix_3_rd_A	2147483647	1197	0	0
prefix_4_rd_A	2147483647	1053	0	0
prefix_5_rd_A	2147483647	1218	0	0
prefix_6_rd_A	2147483647	1198	0	0
prefix_7_rd_A	2147483647	1298	0	0
prefix_8_rd_A	2147483647	1233	0	0
prefix_9_rd_A	2147483647	1211	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	49833	0	0
T52	333733	46047	0	0
T53	0	4	0	0
T54	0	149	0	0
T113	0	2	0	0
T114	0	3	0	0
T115	0	2	0	0
T116	0	113	0	0
T125	0	59	0	0
T128	0	7	0	0
T129	0	61	0	0
T131	23144	0	0	0
T132	742912	0	0	0
T133	6662	0	0	0
T134	972546	0	0	0
T135	23387	0	0	0
T136	144656	0	0	0
T137	6653	0	0	0
T138	17370	0	0	0
T139	431697	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1493	0	0
T99	10990	31	0	0
T101	2802	3	0	0
T102	11233	15	0	0
T105	4523	17	0	0
T113	4218	7	0	0
T148	1728	6	0	0
T149	5104	10	0	0
T150	4186	10	0	0
T151	6014	58	0	0
T152	22348	139	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1962	0	0
T99	10990	30	0	0
T101	2802	3	0	0
T102	11233	39	0	0
T105	4523	11	0	0
T113	4218	14	0	0
T122	1073	2	0	0
T124	1427	25	0	0
T149	5104	7	0	0
T153	1301	23	0	0
T154	1230	32	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1149	0	0
T99	10990	29	0	0
T101	2802	4	0	0
T102	11233	36	0	0
T105	4523	8	0	0
T113	4218	6	0	0
T148	1728	7	0	0
T149	5104	18	0	0
T150	4186	19	0	0
T151	6014	19	0	0
T152	22348	110	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1196	0	0
T99	10990	44	0	0
T101	2802	11	0	0
T102	11233	25	0	0
T105	4523	2	0	0
T113	4218	8	0	0
T148	1728	2	0	0
T149	5104	33	0	0
T150	4186	6	0	0
T151	6014	7	0	0
T152	22348	117	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1144	0	0
T99	10990	28	0	0
T101	2802	18	0	0
T102	11233	29	0	0
T105	4523	4	0	0
T113	4218	8	0	0
T148	1728	7	0	0
T149	5104	13	0	0
T150	4186	13	0	0
T151	6014	25	0	0
T152	22348	90	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1194	0	0
T99	10990	42	0	0
T101	2802	5	0	0
T102	11233	38	0	0
T105	4523	10	0	0
T113	4218	16	0	0
T129	6196	2	0	0
T149	5104	32	0	0
T150	4186	3	0	0
T152	22348	102	0	0
T155	2441	3	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1197	0	0
T99	10990	49	0	0
T101	2802	2	0	0
T102	11233	30	0	0
T105	4523	9	0	0
T113	4218	1	0	0
T116	5359	1	0	0
T149	5104	10	0	0
T150	4186	6	0	0
T151	6014	19	0	0
T152	22348	129	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1053	0	0
T99	10990	17	0	0
T101	2802	7	0	0
T102	11233	27	0	0
T105	4523	19	0	0
T113	4218	5	0	0
T125	6222	1	0	0
T129	6196	2	0	0
T149	5104	6	0	0
T150	4186	11	0	0
T151	6014	23	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1218	0	0
T99	10990	24	0	0
T101	2802	2	0	0
T102	11233	17	0	0
T113	4218	10	0	0
T148	1728	1	0	0
T149	5104	25	0	0
T150	4186	11	0	0
T151	6014	36	0	0
T152	22348	96	0	0
T155	2441	4	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1198	0	0
T99	10990	40	0	0
T101	2802	14	0	0
T102	11233	45	0	0
T105	4523	26	0	0
T113	4218	6	0	0
T148	1728	5	0	0
T149	5104	5	0	0
T150	4186	12	0	0
T151	6014	34	0	0
T152	22348	129	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1298	0	0
T99	10990	24	0	0
T101	2802	6	0	0
T102	11233	45	0	0
T105	4523	13	0	0
T113	4218	6	0	0
T149	5104	41	0	0
T150	4186	13	0	0
T151	6014	29	0	0
T152	22348	171	0	0
T155	2441	1	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1233	0	0
T99	10990	37	0	0
T101	2802	13	0	0
T102	11233	32	0	0
T105	4523	7	0	0
T113	4218	5	0	0
T148	1728	3	0	0
T149	5104	25	0	0
T150	4186	11	0	0
T151	6014	19	0	0
T152	22348	156	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1211	0	0
T99	10990	38	0	0
T101	2802	11	0	0
T102	11233	33	0	0
T105	4523	10	0	0
T113	4218	10	0	0
T148	1728	1	0	0
T149	5104	41	0	0
T150	4186	7	0	0
T151	6014	17	0	0
T152	22348	97	0	0