Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

166100431

1

T1

1004

T2

627

T3

7112

full_word

135414279

1

T1

1261

T2

1415

T3

12045

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	301514440	1			T1	2265		T2	2042		T3	19157
auto[TlIntgErrCmd]	80	1			T110	6		T111	7		T112	3
auto[TlIntgErrData]	96	1			T110	2		T111	6		T112	9
auto[TlIntgErrBoth]	94	1			T110	2		T111	7		T112	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

158276020

1

T1

1311

T2

1067

T3

13083

auto[1]

143238690

1

T1

954

T2

975

T3

6074

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	99694814	1			T1	564		T2	371		T3	4699
auto[TlIntgErrNone]	partial	auto[1]	66405367	1			T1	440		T2	256		T3	2413
auto[TlIntgErrNone]	full_word	auto[0]	58581078	1			T1	747		T2	696		T3	8384
auto[TlIntgErrNone]	full_word	auto[1]	76833181	1			T1	514		T2	719		T3	3661
auto[TlIntgErrCmd]	partial	auto[0]	30	1			T110	1		T111	3		T117	1
auto[TlIntgErrCmd]	partial	auto[1]	43	1			T110	5		T111	4		T112	3
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T117	1		T162	1		T163	1
auto[TlIntgErrCmd]	full_word	auto[1]	2	1			T145	1		T163	1		-	-
auto[TlIntgErrData]	partial	auto[0]	44	1			T111	3		T112	6		T117	1
auto[TlIntgErrData]	partial	auto[1]	44	1			T110	2		T111	3		T112	3
auto[TlIntgErrData]	full_word	auto[0]	4	1			T117	1		T159	1		T164	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T165	1		T166	1		T161	1
auto[TlIntgErrBoth]	partial	auto[0]	43	1			T111	2		T112	3		T117	2
auto[TlIntgErrBoth]	partial	auto[1]	46	1			T110	2		T111	4		T112	4
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T112	1		T166	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T111	1		T117	1		T167	1