Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1446912567	160591	0	0
entropy_period_rd_A	1446912567	1955	0	0
intr_enable_rd_A	1446912567	2707	0	0
prefix_0_rd_A	1446912567	2008	0	0
prefix_10_rd_A	1446912567	1987	0	0
prefix_1_rd_A	1446912567	1927	0	0
prefix_2_rd_A	1446912567	1941	0	0
prefix_3_rd_A	1446912567	1908	0	0
prefix_4_rd_A	1446912567	1978	0	0
prefix_5_rd_A	1446912567	2109	0	0
prefix_6_rd_A	1446912567	2031	0	0
prefix_7_rd_A	1446912567	1903	0	0
prefix_8_rd_A	1446912567	2088	0	0
prefix_9_rd_A	1446912567	1944	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1446912567	160591	0	0
T24	157942	17195	0	0
T33	1058	0	0	0
T50	0	77309	0	0
T51	0	63271	0	0
T108	450494	0	0	0
T109	214975	0	0	0
T110	0	1	0	0
T111	0	2	0	0
T112	0	5	0	0
T116	0	117	0	0
T117	0	2	0	0
T119	0	242	0	0
T120	0	2	0	0
T121	880004	0	0	0
T122	16565	0	0	0
T123	184276	0	0	0
T124	308646	0	0	0
T125	17831	0	0	0
T126	6221	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1446912567	1955	0	0
T94	10628	53	0	0
T98	11075	72	0	0
T100	5767	17	0	0
T110	13172	59	0	0
T118	3955	4	0	0
T120	7663	18	0	0
T128	7317	14	0	0
T138	2964	3	0	0
T139	6889	7	0	0
T140	5744	31	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1446912567	2707	0	0
T94	10628	84	0	0
T110	13172	66	0	0
T113	1046	15	0	0
T118	3955	13	0	0
T120	7663	17	0	0
T128	7317	18	0	0
T138	2964	19	0	0
T141	1173	5	0	0
T142	2381	5	0	0
T143	2303	20	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1446912567	2008	0	0
T94	10628	54	0	0
T98	11075	72	0	0
T100	5767	17	0	0
T110	13172	45	0	0
T120	7663	3	0	0
T128	7317	12	0	0
T138	2964	3	0	0
T139	6889	5	0	0
T140	5744	12	0	0
T144	12079	4	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1446912567	1987	0	0
T94	10628	42	0	0
T98	11075	42	0	0
T100	5767	22	0	0
T110	13172	24	0	0
T120	7663	7	0	0
T128	7317	1	0	0
T138	2964	8	0	0
T139	6889	19	0	0
T140	5744	33	0	0
T142	2381	5	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1446912567	1927	0	0
T94	10628	37	0	0
T98	11075	54	0	0
T100	5767	13	0	0
T110	13172	36	0	0
T120	7663	5	0	0
T128	7317	14	0	0
T138	2964	2	0	0
T139	6889	5	0	0
T140	5744	19	0	0
T145	22844	99	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1446912567	1941	0	0
T94	10628	42	0	0
T98	11075	61	0	0
T100	5767	3	0	0
T110	13172	46	0	0
T120	7663	6	0	0
T128	7317	4	0	0
T138	2964	14	0	0
T139	6889	6	0	0
T140	5744	3	0	0
T142	2381	6	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1446912567	1908	0	0
T94	10628	56	0	0
T98	11075	50	0	0
T100	5767	19	0	0
T110	13172	39	0	0
T118	3955	14	0	0
T120	7663	12	0	0
T138	2964	9	0	0
T139	6889	2	0	0
T140	5744	10	0	0
T145	22844	66	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1446912567	1978	0	0
T94	10628	47	0	0
T98	11075	56	0	0
T100	5767	15	0	0
T110	13172	41	0	0
T120	7663	8	0	0
T128	7317	11	0	0
T138	2964	9	0	0
T139	6889	12	0	0
T140	5744	19	0	0
T142	2381	2	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1446912567	2109	0	0
T94	10628	34	0	0
T98	11075	63	0	0
T100	5767	13	0	0
T110	13172	43	0	0
T118	3955	5	0	0
T120	7663	3	0	0
T128	7317	18	0	0
T138	2964	5	0	0
T139	6889	5	0	0
T142	2381	9	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1446912567	2031	0	0
T94	10628	24	0	0
T98	11075	55	0	0
T100	5767	18	0	0
T110	13172	33	0	0
T118	3955	7	0	0
T120	7663	7	0	0
T128	7317	13	0	0
T138	2964	11	0	0
T139	6889	10	0	0
T142	2381	1	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1446912567	1903	0	0
T94	10628	47	0	0
T98	11075	41	0	0
T100	5767	3	0	0
T110	13172	29	0	0
T120	7663	4	0	0
T128	7317	14	0	0
T138	2964	10	0	0
T139	6889	6	0	0
T140	5744	14	0	0
T142	2381	1	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1446912567	2088	0	0
T94	10628	50	0	0
T98	11075	63	0	0
T100	5767	9	0	0
T110	13172	22	0	0
T118	3955	8	0	0
T120	7663	8	0	0
T128	7317	18	0	0
T138	2964	8	0	0
T139	6889	5	0	0
T142	2381	5	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1446912567	1944	0	0
T94	10628	41	0	0
T98	11075	56	0	0
T100	5767	17	0	0
T110	13172	36	0	0
T118	3955	10	0	0
T120	7663	6	0	0
T128	7317	12	0	0
T138	2964	9	0	0
T139	6889	7	0	0
T142	2381	5	0	0