Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	66338676	1			T1	15606		T3	268		T4	2534
all_values[1]	66338676	1			T1	15606		T3	268		T4	2534
all_values[2]	66338676	1			T1	15606		T3	268		T4	2534

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

431825

1

T1

206

T3

6

T4

74

auto[1]

198584203

1

T1

46612

T3

798

T4

7528

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

198127164

1

T1

46398

T3

759

T4

6891

auto[1]

888864

1

T1

420

T3

45

T4

711

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	147064	1			T4	64		T14	76		T15	136
all_values[0]	auto[0]	auto[1]	1810	1			T4	10		T14	10		T19	2
all_values[0]	auto[1]	auto[0]	65895324	1			T1	15466		T3	253		T4	2233
all_values[0]	auto[1]	auto[1]	294478	1			T1	140		T3	15		T4	227
all_values[1]	auto[0]	auto[0]	136704	1			T1	203		T3	5		T15	136
all_values[1]	auto[0]	auto[1]	1291	1			T1	3		T3	1		T17	3
all_values[1]	auto[1]	auto[0]	65905684	1			T1	15263		T3	248		T4	2297
all_values[1]	auto[1]	auto[1]	294997	1			T1	137		T3	14		T4	237
all_values[2]	auto[0]	auto[0]	143629	1			T14	62		T17	4		T20	458
all_values[2]	auto[0]	auto[1]	1327	1			T14	6		T17	3		T20	5
all_values[2]	auto[1]	auto[0]	65898759	1			T1	15466		T3	253		T4	2297
all_values[2]	auto[1]	auto[1]	294961	1			T1	140		T3	15		T4	237