Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	66338676	1			T1	15606		T3	268		T4	2534
all_pins[1]	66338676	1			T1	15606		T3	268		T4	2534
all_pins[2]	66338676	1			T1	15606		T3	268		T4	2534

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	198430261	1			T1	46479		T3	789		T4	7375
values[0x1]	585767	1			T1	339		T3	15		T4	227
transitions[0x0=>0x1]	583961	1			T1	339		T3	15		T4	227
transitions[0x1=>0x0]	583990	1			T1	339		T3	15		T4	227

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	66044198	1			T1	15466		T3	253		T4	2307
all_pins[0]	values[0x1]	294478	1			T1	140		T3	15		T4	227
all_pins[0]	transitions[0x0=>0x1]	294468	1			T1	140		T3	15		T4	227
all_pins[0]	transitions[0x1=>0x0]	56	1			T42	2		T182	3		T183	2
all_pins[1]	values[0x0]	66338610	1			T1	15606		T3	268		T4	2534
all_pins[1]	values[0x1]	66	1			T42	2		T182	3		T183	2
all_pins[1]	transitions[0x0=>0x1]	49	1			T42	2		T182	3		T183	2
all_pins[1]	transitions[0x1=>0x0]	291206	1			T1	199		T15	70		T23	311
all_pins[2]	values[0x0]	66047453	1			T1	15407		T3	268		T4	2534
all_pins[2]	values[0x1]	291223	1			T1	199		T15	70		T23	311
all_pins[2]	transitions[0x0=>0x1]	289444	1			T1	199		T15	69		T23	311
all_pins[2]	transitions[0x1=>0x0]	292728	1			T1	140		T3	15		T4	227