Summary for Variable share
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 2 | 0 | 2 | 100.00 | 
Automatically Generated Bins for share
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 8063551 | 1 |  |  | T1 | 15344 |  | T3 | 96 |  | T4 | 25322 | 
| auto[1] | 17295035 | 1 |  |  | T1 | 23496 |  | T3 | 450 |  | T4 | 37096 | 
Summary for Variable state_read_mask
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 4 | 0 | 4 | 100.00 | 
User Defined Bins for state_read_mask
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| word_access | 25294741 | 1 |  |  | T1 | 38771 |  | T3 | 546 |  | T4 | 62310 | 
| triple_byte_access | 21278 | 1 |  |  | T1 | 23 |  | T4 | 28 |  | T15 | 3 | 
| halfword_access | 21426 | 1 |  |  | T1 | 23 |  | T4 | 37 |  | T15 | 1 | 
| byte_access | 21141 | 1 |  |  | T1 | 23 |  | T4 | 43 |  | T15 | 4 | 
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 8 | 3 | 5 | 62.50 | 3 | 
Automatically Generated Cross Bins for state_mask_share_cross
Uncovered bins
| share | state_read_mask | COUNT | AT LEAST | NUMBER | STATUS | 
| [auto[1]] | [triple_byte_access , halfword_access , byte_access] | -- | -- | 3 |  | 
Covered bins
| share | state_read_mask | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | word_access | 7999706 | 1 |  |  | T1 | 15275 |  | T3 | 96 |  | T4 | 25214 | 
| auto[0] | triple_byte_access | 21278 | 1 |  |  | T1 | 23 |  | T4 | 28 |  | T15 | 3 | 
| auto[0] | halfword_access | 21426 | 1 |  |  | T1 | 23 |  | T4 | 37 |  | T15 | 1 | 
| auto[0] | byte_access | 21141 | 1 |  |  | T1 | 23 |  | T4 | 43 |  | T15 | 4 | 
| auto[1] | word_access | 17295035 | 1 |  |  | T1 | 23496 |  | T3 | 450 |  | T4 | 37096 |