Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

160268320

1

T1

720

T2

132

T3

67575

full_word

129254174

1

T1

1402

T2

4145

T3

104519

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	289522224	1			T1	2122		T2	4277		T3	172094
auto[TlIntgErrCmd]	92	1			T109	3		T110	5		T111	6
auto[TlIntgErrData]	89	1			T109	3		T110	2		T111	1
auto[TlIntgErrBoth]	89	1			T109	4		T110	3		T111	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

151925644

1

T1

1105

T2

3657

T3

117540

auto[1]

137596850

1

T1

1017

T2

620

T3

54554

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	96115434	1			T1	413		T2	64		T3	43129
auto[TlIntgErrNone]	partial	auto[1]	64152645	1			T1	307		T2	68		T3	24446
auto[TlIntgErrNone]	full_word	auto[0]	55810092	1			T1	692		T2	3593		T3	74411
auto[TlIntgErrNone]	full_word	auto[1]	73444053	1			T1	710		T2	552		T3	30108
auto[TlIntgErrCmd]	partial	auto[0]	39	1			T109	2		T110	2		T111	2
auto[TlIntgErrCmd]	partial	auto[1]	44	1			T109	1		T110	1		T111	3
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T110	2		T162	1		T163	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T111	1		T159	1		T164	1
auto[TlIntgErrData]	partial	auto[0]	41	1			T109	2		T110	2		T111	1
auto[TlIntgErrData]	partial	auto[1]	37	1			T109	1		T161	7		T157	1
auto[TlIntgErrData]	full_word	auto[0]	2	1			T165	1		T164	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	9	1			T157	1		T166	1		T167	1
auto[TlIntgErrBoth]	partial	auto[0]	30	1			T109	1		T110	1		T111	1
auto[TlIntgErrBoth]	partial	auto[1]	50	1			T109	3		T110	2		T111	1
auto[TlIntgErrBoth]	full_word	auto[0]	1	1			T160	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	8	1			T111	1		T157	1		T165	1