Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 174501843 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 142024226 1 T1 16753 T2 32819 T3 261281



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 166280737 1 T1 19024 T2 35253 T3 345123
values[0x0] 72302041 1 T1 3968 T2 8800 T3 156708
values[0x1] 77943291 1 T1 4364 T2 9298 T3 171858



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 136040112 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 180485957 1 T1 19335 T2 37328 T3 353142



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 937981 1 T1 97 T2 211 T14 12
valid_sources[0x01] 1782858 1 T1 128 T2 221 T14 9
valid_sources[0x02] 1816855 1 T1 90 T2 224 T14 7
valid_sources[0x03] 933435 1 T1 93 T2 227 T14 2
valid_sources[0x04] 1385528 1 T1 110 T2 198 T14 12
valid_sources[0x05] 923714 1 T1 101 T2 232 T14 9
valid_sources[0x06] 926428 1 T1 108 T2 218 T14 22
valid_sources[0x07] 931440 1 T1 106 T2 238 T14 7
valid_sources[0x08] 926934 1 T1 108 T2 209 T14 7
valid_sources[0x09] 929502 1 T1 89 T2 253 T14 9
valid_sources[0x0a] 929729 1 T1 85 T2 216 T14 4
valid_sources[0x0b] 3603357 1 T1 102 T2 181 T14 6
valid_sources[0x0c] 949928 1 T1 108 T2 189 T14 7
valid_sources[0x0d] 931242 1 T1 107 T2 207 T14 8
valid_sources[0x0e] 1071888 1 T1 87 T2 209 T14 9
valid_sources[0x0f] 936740 1 T1 92 T2 212 T14 8
valid_sources[0x10] 956729 1 T1 97 T2 207 T14 12
valid_sources[0x11] 954797 1 T1 112 T2 227 T14 7
valid_sources[0x12] 930464 1 T1 106 T2 209 T14 9
valid_sources[0x13] 980596 1 T1 83 T2 213 T14 5
valid_sources[0x14] 928640 1 T1 103 T2 190 T14 7
valid_sources[0x15] 1833867 1 T1 96 T2 219 T14 10
valid_sources[0x16] 922787 1 T1 111 T2 204 T14 7
valid_sources[0x17] 2006652 1 T1 104 T2 233 T14 7
valid_sources[0x18] 920080 1 T1 136 T2 165 T14 3
valid_sources[0x19] 928790 1 T1 107 T2 197 T14 10
valid_sources[0x1a] 1100265 1 T1 107 T2 197 T14 8
valid_sources[0x1b] 1024872 1 T1 80 T2 203 T14 11
valid_sources[0x1c] 919644 1 T1 101 T2 179 T14 5
valid_sources[0x1d] 1043041 1 T1 94 T2 173 T14 12
valid_sources[0x1e] 928104 1 T1 135 T2 212 T14 8
valid_sources[0x1f] 1123287 1 T1 93 T2 227 T14 2
valid_sources[0x20] 991104 1 T1 114 T2 196 T14 9
valid_sources[0x21] 930975 1 T1 99 T2 173 T14 18
valid_sources[0x22] 2640521 1 T1 130 T2 211 T14 9
valid_sources[0x23] 1915855 1 T1 105 T2 180 T14 7
valid_sources[0x24] 927161 1 T1 96 T2 201 T14 14
valid_sources[0x25] 944526 1 T1 96 T2 200 T14 8
valid_sources[0x26] 1149777 1 T1 114 T2 216 T14 16
valid_sources[0x27] 1943147 1 T1 96 T2 201 T14 11
valid_sources[0x28] 932349 1 T1 114 T2 200 T14 7
valid_sources[0x29] 1583759 1 T1 91 T2 196 T14 6
valid_sources[0x2a] 1055722 1 T1 94 T2 200 T14 6
valid_sources[0x2b] 1072255 1 T1 109 T2 210 T14 11
valid_sources[0x2c] 1061906 1 T1 114 T2 189 T14 10
valid_sources[0x2d] 1873838 1 T1 102 T2 233 T14 11
valid_sources[0x2e] 921435 1 T1 94 T2 208 T14 6
valid_sources[0x2f] 1791256 1 T1 112 T2 198 T14 8
valid_sources[0x30] 932185 1 T1 98 T2 230 T14 3
valid_sources[0x31] 1818931 1 T1 103 T2 221 T14 6
valid_sources[0x32] 1382544 1 T1 103 T2 218 T14 11
valid_sources[0x33] 1879985 1 T1 127 T2 215 T14 4
valid_sources[0x34] 1395844 1 T1 107 T2 203 T14 8
valid_sources[0x35] 929317 1 T1 101 T2 186 T14 7
valid_sources[0x36] 921333 1 T1 109 T2 241 T14 12
valid_sources[0x37] 958807 1 T1 98 T2 207 T14 9
valid_sources[0x38] 928725 1 T1 89 T2 195 T14 4
valid_sources[0x39] 1023836 1 T1 117 T2 205 T14 7
valid_sources[0x3a] 925906 1 T1 109 T2 195 T14 7
valid_sources[0x3b] 926677 1 T1 100 T2 192 T14 12
valid_sources[0x3c] 934462 1 T1 100 T2 252 T14 11
valid_sources[0x3d] 1029937 1 T1 118 T2 212 T14 11
valid_sources[0x3e] 935530 1 T1 113 T2 223 T14 11
valid_sources[0x3f] 926390 1 T1 122 T2 216 T14 15
valid_sources[0x40] 966293 1 T1 117 T2 222 T14 8
valid_sources[0x41] 939509 1 T1 79 T2 164 T14 8
valid_sources[0x42] 929398 1 T1 100 T2 206 T14 16
valid_sources[0x43] 1578416 1 T1 113 T2 191 T14 6
valid_sources[0x44] 925602 1 T1 112 T2 193 T14 6
valid_sources[0x45] 1400735 1 T1 109 T2 230 T14 7
valid_sources[0x46] 935270 1 T1 128 T2 217 T14 5
valid_sources[0x47] 926809 1 T1 127 T2 184 T14 6
valid_sources[0x48] 941673 1 T1 123 T2 208 T14 13
valid_sources[0x49] 947044 1 T1 106 T2 200 T14 8
valid_sources[0x4a] 936077 1 T1 105 T2 200 T14 7
valid_sources[0x4b] 925698 1 T1 116 T2 192 T14 9
valid_sources[0x4c] 1610943 1 T1 104 T2 215 T14 9
valid_sources[0x4d] 924251 1 T1 91 T2 230 T14 7
valid_sources[0x4e] 927458 1 T1 116 T2 186 T14 9
valid_sources[0x4f] 932702 1 T1 110 T2 247 T14 1
valid_sources[0x50] 919488 1 T1 109 T2 224 T14 11
valid_sources[0x51] 1055085 1 T1 101 T2 224 T14 3
valid_sources[0x52] 1850598 1 T1 99 T2 192 T14 5
valid_sources[0x53] 1594086 1 T1 133 T2 233 T14 3
valid_sources[0x54] 938511 1 T1 105 T2 225 T14 4
valid_sources[0x55] 965424 1 T1 102 T2 209 T14 7
valid_sources[0x56] 2337065 1 T1 93 T2 191 T14 7
valid_sources[0x57] 976616 1 T1 96 T2 218 T14 8
valid_sources[0x58] 923393 1 T1 73 T2 220 T14 7
valid_sources[0x59] 989174 1 T1 114 T2 207 T14 6
valid_sources[0x5a] 3240287 1 T1 80 T2 178 T14 11
valid_sources[0x5b] 987691 1 T1 105 T2 189 T14 8
valid_sources[0x5c] 946234 1 T1 124 T2 218 T14 5
valid_sources[0x5d] 978702 1 T1 104 T2 220 T14 7
valid_sources[0x5e] 3397861 1 T1 94 T2 223 T14 6
valid_sources[0x5f] 1203948 1 T1 99 T2 221 T14 7
valid_sources[0x60] 1503986 1 T1 114 T2 227 T14 11
valid_sources[0x61] 1600746 1 T1 113 T2 174 T14 12
valid_sources[0x62] 1483123 1 T1 101 T2 215 T14 5
valid_sources[0x63] 1384040 1 T1 102 T2 209 T14 10
valid_sources[0x64] 925767 1 T1 115 T2 222 T14 9
valid_sources[0x65] 926099 1 T1 118 T2 202 T14 7
valid_sources[0x66] 919166 1 T1 116 T2 192 T14 4
valid_sources[0x67] 930823 1 T1 107 T2 205 T14 8
valid_sources[0x68] 1504065 1 T1 109 T2 205 T14 6
valid_sources[0x69] 930287 1 T1 106 T2 243 T14 6
valid_sources[0x6a] 1724443 1 T1 97 T2 208 T14 7
valid_sources[0x6b] 921674 1 T1 88 T2 180 T14 8
valid_sources[0x6c] 926353 1 T1 110 T2 213 T14 7
valid_sources[0x6d] 934081 1 T1 100 T2 220 T14 10
valid_sources[0x6e] 1625856 1 T1 113 T2 207 T14 14
valid_sources[0x6f] 3420383 1 T1 112 T2 194 T14 7
valid_sources[0x70] 930828 1 T1 101 T2 214 T14 7
valid_sources[0x71] 940853 1 T1 110 T2 230 T14 8
valid_sources[0x72] 934107 1 T1 108 T2 203 T14 9
valid_sources[0x73] 926211 1 T1 134 T2 237 T14 14
valid_sources[0x74] 1207321 1 T1 111 T2 224 T14 9
valid_sources[0x75] 949877 1 T1 101 T2 212 T14 7
valid_sources[0x76] 926804 1 T1 113 T2 218 T14 5
valid_sources[0x77] 1101866 1 T1 102 T2 206 T14 11
valid_sources[0x78] 1102711 1 T1 106 T2 203 T14 17
valid_sources[0x79] 928459 1 T1 87 T2 223 T14 8
valid_sources[0x7a] 930950 1 T1 102 T2 198 T14 7
valid_sources[0x7b] 1187502 1 T1 105 T2 185 T14 10
valid_sources[0x7c] 1377976 1 T1 131 T2 210 T14 11
valid_sources[0x7d] 927953 1 T1 97 T2 184 T14 11
valid_sources[0x7e] 927067 1 T1 95 T2 205 T14 11
valid_sources[0x7f] 934850 1 T1 119 T2 223 T14 8
valid_sources[0x80] 966431 1 T1 93 T2 195 T14 14



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 61175192 1 T1 12423 T2 22837 T3 100784
values[0x0] all_enables biggest_size 43349152 1 T1 2329 T2 5348 T3 87007
values[0x1] all_enables biggest_size 37499882 1 T1 2001 T2 4634 T3 73490

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%