Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

174949232

1

T1

10603

T2

20532

T3

412408

full_word

142052085

1

T1

16753

T2

32819

T3

261281

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	317000997	1			T1	27356		T2	53351		T3	673689
auto[TlIntgErrCmd]	105	1			T113	2		T116	4		T117	9
auto[TlIntgErrData]	108	1			T113	6		T116	8		T117	4
auto[TlIntgErrBoth]	107	1			T113	2		T116	8		T117	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

166387705

1

T1

19024

T2

35253

T3

345123

auto[1]

150613612

1

T1

8332

T2

18098

T3

328566

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	105204205	1			T1	6601		T2	12416		T3	244339
auto[TlIntgErrNone]	partial	auto[1]	69744740	1			T1	4002		T2	8116		T3	168069
auto[TlIntgErrNone]	full_word	auto[0]	61183358	1			T1	12423		T2	22837		T3	100784
auto[TlIntgErrNone]	full_word	auto[1]	80868694	1			T1	4330		T2	9982		T3	160497
auto[TlIntgErrCmd]	partial	auto[0]	35	1			T116	4		T117	2		T127	2
auto[TlIntgErrCmd]	partial	auto[1]	60	1			T113	1		T117	5		T127	3
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T117	1		T170	2		T168	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T113	1		T117	1		T171	1
auto[TlIntgErrData]	partial	auto[0]	50	1			T113	1		T116	2		T117	3
auto[TlIntgErrData]	partial	auto[1]	46	1			T113	4		T116	4		T127	1
auto[TlIntgErrData]	full_word	auto[0]	9	1			T113	1		T116	2		T117	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T172	1		T173	1		T174	1
auto[TlIntgErrBoth]	partial	auto[0]	38	1			T113	2		T116	4		T117	2
auto[TlIntgErrBoth]	partial	auto[1]	58	1			T116	4		T117	4		T127	2
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T117	1		T167	1		T171	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T131	2		T169	2		T175	1