Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	175520559	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

140671490

1

T1

261567

T2

888669

T3

6089

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	166676070	1			T1	342095		T2	109490		T3	4796
values[0x0]	71882958	1			T1	155650		T2	443993		T3	1201
values[0x1]	77633021	1			T1	169904		T2	473474		T3	1178

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	136807134	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

179384915

1

T1

350742

T2

113272

T3

6371

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	991091	1			T1	2595		T2	7840		T3	23
valid_sources[0x01]	938335	1			T1	2399		T2	7745		T3	24
valid_sources[0x02]	3359878	1			T1	2505		T2	7756		T3	37
valid_sources[0x03]	944528	1			T1	2714		T2	7755		T3	32
valid_sources[0x04]	938174	1			T1	2771		T2	7839		T3	24
valid_sources[0x05]	946220	1			T1	2643		T2	8008		T3	33
valid_sources[0x06]	1975256	1			T1	2669		T2	7551		T3	31
valid_sources[0x07]	943478	1			T1	2626		T2	7647		T3	37
valid_sources[0x08]	946693	1			T1	2605		T2	8251		T3	20
valid_sources[0x09]	937538	1			T1	2654		T2	7639		T3	24
valid_sources[0x0a]	1186555	1			T1	2614		T2	7608		T3	18
valid_sources[0x0b]	943806	1			T1	2677		T2	7891		T3	18
valid_sources[0x0c]	944435	1			T1	2506		T2	8178		T3	22
valid_sources[0x0d]	943903	1			T1	2542		T2	7861		T3	37
valid_sources[0x0e]	976461	1			T1	2363		T2	7953		T3	23
valid_sources[0x0f]	939855	1			T1	2504		T2	7592		T3	19
valid_sources[0x10]	938903	1			T1	2464		T2	7896		T3	25
valid_sources[0x11]	939100	1			T1	2541		T2	8021		T3	24
valid_sources[0x12]	940287	1			T1	2668		T2	7983		T3	33
valid_sources[0x13]	944125	1			T1	2757		T2	7603		T3	34
valid_sources[0x14]	943708	1			T1	2627		T2	8004		T3	24
valid_sources[0x15]	1074645	1			T1	2581		T2	7948		T3	19
valid_sources[0x16]	943861	1			T1	2785		T2	8060		T3	37
valid_sources[0x17]	943818	1			T1	2607		T2	7786		T3	30
valid_sources[0x18]	942191	1			T1	2644		T2	8027		T3	23
valid_sources[0x19]	942421	1			T1	2587		T2	7494		T3	27
valid_sources[0x1a]	943113	1			T1	2542		T2	7888		T3	22
valid_sources[0x1b]	944790	1			T1	2599		T2	7557		T3	31
valid_sources[0x1c]	938451	1			T1	2610		T2	7888		T3	29
valid_sources[0x1d]	942910	1			T1	2612		T2	7664		T3	35
valid_sources[0x1e]	1400313	1			T1	2585		T2	7293		T3	30
valid_sources[0x1f]	949183	1			T1	2607		T2	7691		T3	20
valid_sources[0x20]	937865	1			T1	2529		T2	7483		T3	45
valid_sources[0x21]	943144	1			T1	2628		T2	7672		T3	25
valid_sources[0x22]	1023163	1			T1	2613		T2	7674		T3	22
valid_sources[0x23]	937782	1			T1	2570		T2	7760		T3	26
valid_sources[0x24]	1624526	1			T1	2641		T2	7809		T3	40
valid_sources[0x25]	976590	1			T1	2569		T2	7960		T3	30
valid_sources[0x26]	1412773	1			T1	2571		T2	7991		T3	29
valid_sources[0x27]	969042	1			T1	2543		T2	7885		T3	23
valid_sources[0x28]	3445251	1			T1	2587		T2	7766		T3	24
valid_sources[0x29]	967022	1			T1	2638		T2	7813		T3	32
valid_sources[0x2a]	941854	1			T1	2777		T2	7639		T3	34
valid_sources[0x2b]	947975	1			T1	2604		T2	7635		T3	21
valid_sources[0x2c]	940813	1			T1	2578		T2	7741		T3	26
valid_sources[0x2d]	948243	1			T1	2660		T2	7918		T3	32
valid_sources[0x2e]	998806	1			T1	2466		T2	7931		T3	28
valid_sources[0x2f]	940697	1			T1	2589		T2	7724		T3	34
valid_sources[0x30]	2716542	1			T1	2547		T2	7935		T3	26
valid_sources[0x31]	946516	1			T1	2854		T2	7911		T3	30
valid_sources[0x32]	940520	1			T1	2835		T2	8298		T3	16
valid_sources[0x33]	940457	1			T1	2594		T2	7892		T3	34
valid_sources[0x34]	1081237	1			T1	2595		T2	7835		T3	32
valid_sources[0x35]	946847	1			T1	2719		T2	7864		T3	13
valid_sources[0x36]	937105	1			T1	2393		T2	7758		T3	29
valid_sources[0x37]	940063	1			T1	2546		T2	7927		T3	24
valid_sources[0x38]	1847217	1			T1	2536		T2	8105		T3	25
valid_sources[0x39]	940563	1			T1	2636		T2	7810		T3	17
valid_sources[0x3a]	1400917	1			T1	2534		T2	7901		T3	29
valid_sources[0x3b]	1001382	1			T1	2589		T2	8193		T3	28
valid_sources[0x3c]	943314	1			T1	2700		T2	8121		T3	31
valid_sources[0x3d]	941380	1			T1	2618		T2	7656		T3	32
valid_sources[0x3e]	1618245	1			T1	2586		T2	7893		T3	24
valid_sources[0x3f]	1008184	1			T1	2456		T2	8067		T3	29
valid_sources[0x40]	1414235	1			T1	2539		T2	7910		T3	28
valid_sources[0x41]	947246	1			T1	2540		T2	8204		T3	28
valid_sources[0x42]	3414483	1			T1	2573		T2	7788		T3	30
valid_sources[0x43]	1803694	1			T1	2564		T2	8075		T3	19
valid_sources[0x44]	1599956	1			T1	2795		T2	8003		T3	25
valid_sources[0x45]	1009645	1			T1	2425		T2	8428		T3	34
valid_sources[0x46]	946800	1			T1	2568		T2	8017		T3	26
valid_sources[0x47]	1819573	1			T1	2628		T2	7895		T3	27
valid_sources[0x48]	941554	1			T1	2529		T2	7889		T3	24
valid_sources[0x49]	963142	1			T1	2750		T2	7834		T3	16
valid_sources[0x4a]	935389	1			T1	2596		T2	7576		T3	36
valid_sources[0x4b]	940289	1			T1	2699		T2	7472		T3	22
valid_sources[0x4c]	938566	1			T1	2443		T2	8113		T3	22
valid_sources[0x4d]	939811	1			T1	2434		T2	7602		T3	45
valid_sources[0x4e]	940462	1			T1	2848		T2	7726		T3	17
valid_sources[0x4f]	950414	1			T1	2739		T2	7706		T3	29
valid_sources[0x50]	942613	1			T1	2737		T2	7846		T3	25
valid_sources[0x51]	941812	1			T1	2599		T2	7559		T3	30
valid_sources[0x52]	942593	1			T1	2451		T2	7647		T3	30
valid_sources[0x53]	936223	1			T1	2761		T2	7863		T3	33
valid_sources[0x54]	1399429	1			T1	2680		T2	7875		T3	19
valid_sources[0x55]	1103736	1			T1	2538		T2	7681		T3	17
valid_sources[0x56]	938117	1			T1	2934		T2	8014		T3	33
valid_sources[0x57]	1406603	1			T1	2647		T2	7780		T3	23
valid_sources[0x58]	932345	1			T1	2665		T2	7545		T3	24
valid_sources[0x59]	945601	1			T1	2619		T2	8252		T3	22
valid_sources[0x5a]	1073692	1			T1	2456		T2	7963		T3	28
valid_sources[0x5b]	1517118	1			T1	2645		T2	8155		T3	36
valid_sources[0x5c]	1003100	1			T1	2564		T2	8180		T3	16
valid_sources[0x5d]	942876	1			T1	2679		T2	7798		T3	25
valid_sources[0x5e]	1843569	1			T1	2729		T2	7589		T3	21
valid_sources[0x5f]	941628	1			T1	2744		T2	7792		T3	40
valid_sources[0x60]	3000312	1			T1	2490		T2	8082		T3	39
valid_sources[0x61]	940922	1			T1	2598		T2	7896		T3	31
valid_sources[0x62]	1197357	1			T1	2499		T2	8000		T3	28
valid_sources[0x63]	1124509	1			T1	2467		T2	7760		T3	34
valid_sources[0x64]	951555	1			T1	2660		T2	8057		T3	37
valid_sources[0x65]	943236	1			T1	2553		T2	7520		T3	37
valid_sources[0x66]	938072	1			T1	2604		T2	7788		T3	28
valid_sources[0x67]	1871192	1			T1	2648		T2	7761		T3	31
valid_sources[0x68]	1161282	1			T1	2513		T2	8148		T3	27
valid_sources[0x69]	1865052	1			T1	2560		T2	7751		T3	45
valid_sources[0x6a]	939776	1			T1	2655		T2	8178		T3	18
valid_sources[0x6b]	941412	1			T1	2389		T2	7876		T3	36
valid_sources[0x6c]	1097405	1			T1	2594		T2	7884		T3	20
valid_sources[0x6d]	1399379	1			T1	2791		T2	7918		T3	20
valid_sources[0x6e]	1598152	1			T1	2693		T2	7887		T3	19
valid_sources[0x6f]	1640355	1			T1	2510		T2	7612		T3	32
valid_sources[0x70]	943347	1			T1	2725		T2	7657		T3	29
valid_sources[0x71]	1401112	1			T1	2729		T2	7700		T3	36
valid_sources[0x72]	1496936	1			T1	2633		T2	8048		T3	24
valid_sources[0x73]	1391826	1			T1	2576		T2	7898		T3	20
valid_sources[0x74]	943432	1			T1	2730		T2	7768		T3	29
valid_sources[0x75]	1067613	1			T1	2569		T2	7960		T3	44
valid_sources[0x76]	1004859	1			T1	2583		T2	7983		T3	26
valid_sources[0x77]	940688	1			T1	2611		T2	7828		T3	28
valid_sources[0x78]	934938	1			T1	2457		T2	8069		T3	37
valid_sources[0x79]	945051	1			T1	2705		T2	7788		T3	30
valid_sources[0x7a]	941744	1			T1	2551		T2	7656		T3	26
valid_sources[0x7b]	1032194	1			T1	2719		T2	7391		T3	23
valid_sources[0x7c]	936825	1			T1	2489		T2	8031		T3	28
valid_sources[0x7d]	2123585	1			T1	2634		T2	8065		T3	31
valid_sources[0x7e]	943184	1			T1	2425		T2	7887		T3	19
valid_sources[0x7f]	1384689	1			T1	2491		T2	7652		T3	34
valid_sources[0x80]	1416647	1			T1	2478		T2	7657		T3	24

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

61185522

1

T1

100024

T2

414702

T3

4196

values[0x0]

all_enables

biggest_size

42682481

1

T1

87330

T2

257066

T3

971

values[0x1]

all_enables

biggest_size

36803487

1

T1

74213

T2

216901

T3

922