Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

175846357

1

T1

406082

T2

112370

T3

1086

full_word

140691858

1

T1

261567

T2

888669

T3

6089

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	316537875	1			T1	667649		T2	201237		T3	7175
auto[TlIntgErrCmd]	117	1			T117	2		T118	8		T119	7
auto[TlIntgErrData]	100	1			T117	3		T118	3		T179	9
auto[TlIntgErrBoth]	123	1			T117	5		T118	9		T119	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

166751426

1

T1

342095

T2

109490

T3

4796

auto[1]

149786789

1

T1

325554

T2

917467

T3

2379

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	105560064	1			T1	242071		T2	680207		T3	600
auto[TlIntgErrNone]	partial	auto[1]	70285984	1			T1	164011		T2	443500		T3	486
auto[TlIntgErrNone]	full_word	auto[0]	61191204	1			T1	100024		T2	414702		T3	4196
auto[TlIntgErrNone]	full_word	auto[1]	79500623	1			T1	161543		T2	473967		T3	1893
auto[TlIntgErrCmd]	partial	auto[0]	49	1			T117	1		T118	4		T119	4
auto[TlIntgErrCmd]	partial	auto[1]	57	1			T117	1		T118	4		T119	3
auto[TlIntgErrCmd]	full_word	auto[0]	7	1			T152	1		T180	1		T178	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T181	1		T182	1		T183	2
auto[TlIntgErrData]	partial	auto[0]	48	1			T117	1		T118	2		T179	4
auto[TlIntgErrData]	partial	auto[1]	43	1			T117	2		T179	4		T152	3
auto[TlIntgErrData]	full_word	auto[0]	6	1			T179	1		T177	1		T178	3
auto[TlIntgErrData]	full_word	auto[1]	3	1			T118	1		T178	1		T125	1
auto[TlIntgErrBoth]	partial	auto[0]	42	1			T117	1		T118	2		T119	2
auto[TlIntgErrBoth]	partial	auto[1]	70	1			T117	3		T118	7		T119	1
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T181	2		T178	1		T183	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T117	1		T177	1		T182	1