Unified Coverage Report :: Module :: tlul_rsp_intg_gen

Module : tlul_rsp_intg_gen

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.83	91.67					100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen	83.33	66.67					100.00
tb.dut.u_tlul_adapter_msgfifo.u_rsp_gen	91.67	83.33					100.00
tb.dut.u_staterd.u_tlul_adapter.u_rsp_gen	91.67	83.33					100.00
tb.dut.u_reg.u_rsp_intg_gen	100.00	100.00					100.00
tb.dut.u_reg.u_socket.gen_err_resp.err_resp.u_intg_gen	100.00	100.00					100.00

---

Module Instance : tb.dut.u_reg.u_reg_if.u_rsp_intg_gen

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.33	66.67					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.33	66.67					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.98	100.00	95.92			100.00	100.00	u_reg_if

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_tlul_adapter_msgfifo.u_rsp_gen

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.67	83.33					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.67	83.33					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
85.43	98.55	77.78			80.77	84.62	u_tlul_adapter_msgfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_staterd.u_tlul_adapter.u_rsp_gen

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.67	83.33					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.67	83.33					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.56	98.61	83.33			92.31	100.00	u_tlul_adapter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_rsp_intg_gen

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.93	100.00	99.73			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_data_intg.u_tlul_data_integ_enc	100.00	100.00
gen_rsp_intg.u_rsp_gen	100.00	100.00

---

Module Instance : tb.dut.u_reg.u_socket.gen_err_resp.err_resp.u_intg_gen

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
57.14	71.43	50.00			50.00		gen_err_resp.err_resp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_data_intg.u_tlul_data_integ_enc	100.00	100.00
gen_rsp_intg.u_rsp_gen	100.00	100.00

Line Coverage for Module : tlul_rsp_intg_gen ( parameter EnableRspIntgGen=0,EnableDataIntgGen=0 )
Line Coverage for Module self-instances :

SCORE	LINE
91.67	83.33

tb.dut.u_tlul_adapter_msgfifo.u_rsp_gen

SCORE	LINE
91.67	83.33

tb.dut.u_staterd.u_tlul_adapter.u_rsp_gen

SCORE	LINE
83.33	66.67

tb.dut.u_reg.u_reg_if.u_rsp_intg_gen

	Line No.	Total	Covered	Percent
TOTAL		6	5	83.33
CONT_ASSIGN	32	1	0	0.00
CONT_ASSIGN	43	1	1	100.00
ALWAYS	47	3	3	100.00
CONT_ASSIGN	53	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
32	0	1
43	1	1
47	1	1
48	1	1
49	1	1
53	1	1

---

Line Coverage for Module : tlul_rsp_intg_gen ( parameter EnableRspIntgGen=1,EnableDataIntgGen=1 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_rsp_intg_gen

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_socket.gen_err_resp.err_resp.u_intg_gen

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	25	1	1	100.00
ALWAYS	47	3	3	100.00
CONT_ASSIGN	53	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
47	1	1
48	1	1
49	1	1
53	1	1

---

Assert Coverage for Module : tlul_rsp_intg_gen

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataWidthCheck_A	5425	5425	0	0
PayLoadWidthCheck	5425	5425	0	0

DataWidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5425	5425	0	0
T1	5	5	0	0
T2	5	5	0	0
T3	5	5	0	0
T13	5	5	0	0
T14	5	5	0	0
T15	5	5	0	0
T16	5	5	0	0
T17	5	5	0	0
T18	5	5	0	0
T19	5	5	0	0

PayLoadWidthCheck

Name	Attempts	Real Successes	Failures	Incomplete
Total	5425	5425	0	0
T1	5	5	0	0
T2	5	5	0	0
T3	5	5	0	0
T13	5	5	0	0
T14	5	5	0	0
T15	5	5	0	0
T16	5	5	0	0
T17	5	5	0	0
T18	5	5	0	0
T19	5	5	0	0

Line Coverage for Instance : tb.dut.u_reg.u_reg_if.u_rsp_intg_gen

	Line No.	Total	Covered	Percent
TOTAL		6	4	66.67
CONT_ASSIGN	32	1	0	0.00
CONT_ASSIGN	43	1	0	0.00
ALWAYS	47	3	3	100.00
CONT_ASSIGN	53	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
32	0	1
43	0	1
47	1	1
48	1	1
49	1	1
53	1	1

---

Assert Coverage for Instance : tb.dut.u_reg.u_reg_if.u_rsp_intg_gen

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataWidthCheck_A	1171	1171	0	0
PayLoadWidthCheck	1171	1171	0	0

DataWidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171	1171	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

PayLoadWidthCheck

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171	1171	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_rsp_gen

	Line No.	Total	Covered	Percent
TOTAL		6	5	83.33
CONT_ASSIGN	32	1	0	0.00
CONT_ASSIGN	43	1	1	100.00
ALWAYS	47	3	3	100.00
CONT_ASSIGN	53	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
32	0	1
43	1	1
47	1	1
48	1	1
49	1	1
53	1	1

---

Assert Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_rsp_gen

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataWidthCheck_A	956	956	0	0
PayLoadWidthCheck	956	956	0	0

DataWidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

PayLoadWidthCheck

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_rsp_gen

	Line No.	Total	Covered	Percent
TOTAL		6	5	83.33
CONT_ASSIGN	32	1	0	0.00
CONT_ASSIGN	43	1	1	100.00
ALWAYS	47	3	3	100.00
CONT_ASSIGN	53	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
32	0	1
43	1	1
47	1	1
48	1	1
49	1	1
53	1	1

---

Assert Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_rsp_gen

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataWidthCheck_A	956	956	0	0
PayLoadWidthCheck	956	956	0	0

DataWidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

PayLoadWidthCheck

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_rsp_intg_gen

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	25	1	1	100.00
ALWAYS	47	3	3	100.00
CONT_ASSIGN	53	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
47	1	1
48	1	1
49	1	1
53	1	1

---

Assert Coverage for Instance : tb.dut.u_reg.u_rsp_intg_gen

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataWidthCheck_A	1171	1171	0	0
PayLoadWidthCheck	1171	1171	0	0

DataWidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171	1171	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

PayLoadWidthCheck

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171	1171	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_err_resp.err_resp.u_intg_gen

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	25	1	1	100.00
ALWAYS	47	3	3	100.00
CONT_ASSIGN	53	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
47	1	1
48	1	1
49	1	1
53	1	1

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_err_resp.err_resp.u_intg_gen

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataWidthCheck_A	1171	1171	0	0
PayLoadWidthCheck	1171	1171	0	0

DataWidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171	1171	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

PayLoadWidthCheck

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171	1171	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0