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Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 gen_dfifo[2].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
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Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 gen_dfifo[2].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
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Module Instances:
tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo
tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo
Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
DataKnown_A 1489078454 213891511 0 0
DepthKnown_A 1489078454 1488886581 0 0
RvalidKnown_A 1489078454 1488886581 0 0
WreadyKnown_A 1489078454 1488886581 0 0
gen_passthru_fifo.paramCheckPass 1171 1171 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1489078454 213891511 0 0
T1 610624 487612 0 0
T2 425376 137859 0 0
T3 82420 3075 0 0
T13 775942 621632 0 0
T14 418178 98643 0 0
T15 658962 391907 0 0
T16 24189 1325 0 0
T17 134223 479125 0 0
T18 433309 140980 0 0
T19 148991 6042 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1489078454 1488886581 0 0
T1 610624 610618 0 0
T2 425376 425368 0 0
T3 82420 82350 0 0
T13 775942 775936 0 0
T14 418178 418114 0 0
T15 658962 658924 0 0
T16 24189 24132 0 0
T17 134223 134218 0 0
T18 433309 433300 0 0
T19 148991 148908 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1489078454 1488886581 0 0
T1 610624 610618 0 0
T2 425376 425368 0 0
T3 82420 82350 0 0
T13 775942 775936 0 0
T14 418178 418114 0 0
T15 658962 658924 0 0
T16 24189 24132 0 0
T17 134223 134218 0 0
T18 433309 433300 0 0
T19 148991 148908 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1489078454 1488886581 0 0
T1 610624 610618 0 0
T2 425376 425368 0 0
T3 82420 82350 0 0
T13 775942 775936 0 0
T14 418178 418114 0 0
T15 658962 658924 0 0
T16 24189 24132 0 0
T17 134223 134218 0 0
T18 433309 433300 0 0
T19 148991 148908 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 1171 1171 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
DataKnown_A 1489078454 323135322 0 0
DepthKnown_A 1489078454 1488886581 0 0
RvalidKnown_A 1489078454 1488886581 0 0
WreadyKnown_A 1489078454 1488886581 0 0
gen_passthru_fifo.paramCheckPass 1171 1171 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1489078454 323135322 0 0
T1 610624 150944 0 0
T2 425376 137859 0 0
T3 82420 13861 0 0
T13 775942 192735 0 0
T14 418178 98643 0 0
T15 658962 179701 0 0
T16 24189 5911 0 0
T17 134223 479125 0 0
T18 433309 140980 0 0
T19 148991 18811 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1489078454 1488886581 0 0
T1 610624 610618 0 0
T2 425376 425368 0 0
T3 82420 82350 0 0
T13 775942 775936 0 0
T14 418178 418114 0 0
T15 658962 658924 0 0
T16 24189 24132 0 0
T17 134223 134218 0 0
T18 433309 433300 0 0
T19 148991 148908 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1489078454 1488886581 0 0
T1 610624 610618 0 0
T2 425376 425368 0 0
T3 82420 82350 0 0
T13 775942 775936 0 0
T14 418178 418114 0 0
T15 658962 658924 0 0
T16 24189 24132 0 0
T17 134223 134218 0 0
T18 433309 433300 0 0
T19 148991 148908 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1489078454 1488886581 0 0
T1 610624 610618 0 0
T2 425376 425368 0 0
T3 82420 82350 0 0
T13 775942 775936 0 0
T14 418178 418114 0 0
T15 658962 658924 0 0
T16 24189 24132 0 0
T17 134223 134218 0 0
T18 433309 433300 0 0
T19 148991 148908 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 1171 1171 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0