Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1489078454	57249	0	0
entropy_period_rd_A	1489078454	2303	0	0
intr_enable_rd_A	1489078454	2873	0	0
prefix_0_rd_A	1489078454	1933	0	0
prefix_10_rd_A	1489078454	2079	0	0
prefix_1_rd_A	1489078454	2029	0	0
prefix_2_rd_A	1489078454	1912	0	0
prefix_3_rd_A	1489078454	2029	0	0
prefix_4_rd_A	1489078454	1876	0	0
prefix_5_rd_A	1489078454	1996	0	0
prefix_6_rd_A	1489078454	1840	0	0
prefix_7_rd_A	1489078454	1904	0	0
prefix_8_rd_A	1489078454	2006	0	0
prefix_9_rd_A	1489078454	1967	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1489078454	57249	0	0
T50	256154	20182	0	0
T51	0	33724	0	0
T52	0	232	0	0
T117	0	2	0	0
T118	0	7	0	0
T119	0	3	0	0
T121	0	208	0	0
T126	0	177	0	0
T128	0	2	0	0
T130	0	71	0	0
T131	331782	0	0	0
T132	337937	0	0	0
T133	30022	0	0	0
T134	271133	0	0	0
T135	852	0	0	0
T136	190439	0	0	0
T137	1548	0	0	0
T138	156618	0	0	0
T139	177810	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1489078454	2303	0	0
T50	256154	64	0	0
T106	0	32	0	0
T110	0	36	0	0
T119	0	81	0	0
T129	0	13	0	0
T131	331782	0	0	0
T132	337937	0	0	0
T133	30022	0	0	0
T134	271133	0	0	0
T135	852	0	0	0
T136	190439	0	0	0
T137	1548	0	0	0
T138	156618	0	0	0
T139	177810	0	0	0
T150	0	15	0	0
T151	0	1	0	0
T152	0	43	0	0
T153	0	17	0	0
T154	0	18	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1489078454	2873	0	0
T50	256154	91	0	0
T119	0	90	0	0
T123	0	7	0	0
T129	0	10	0	0
T131	331782	0	0	0
T132	337937	0	0	0
T133	30022	0	0	0
T134	271133	0	0	0
T135	852	0	0	0
T136	190439	0	0	0
T137	1548	0	0	0
T138	156618	0	0	0
T139	177810	0	0	0
T150	0	28	0	0
T151	0	7	0	0
T155	0	28	0	0
T156	0	26	0	0
T157	0	2	0	0
T158	0	30	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1489078454	1933	0	0
T50	256154	90	0	0
T106	0	37	0	0
T110	0	16	0	0
T119	0	33	0	0
T129	0	4	0	0
T131	331782	0	0	0
T132	337937	0	0	0
T133	30022	0	0	0
T134	271133	0	0	0
T135	852	0	0	0
T136	190439	0	0	0
T137	1548	0	0	0
T138	156618	0	0	0
T139	177810	0	0	0
T150	0	14	0	0
T151	0	5	0	0
T152	0	36	0	0
T153	0	13	0	0
T154	0	11	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1489078454	2079	0	0
T50	256154	67	0	0
T106	0	41	0	0
T110	0	30	0	0
T119	0	37	0	0
T129	0	14	0	0
T131	331782	0	0	0
T132	337937	0	0	0
T133	30022	0	0	0
T134	271133	0	0	0
T135	852	0	0	0
T136	190439	0	0	0
T137	1548	0	0	0
T138	156618	0	0	0
T139	177810	0	0	0
T150	0	17	0	0
T151	0	5	0	0
T152	0	12	0	0
T153	0	23	0	0
T154	0	2	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1489078454	2029	0	0
T50	256154	36	0	0
T106	0	34	0	0
T110	0	11	0	0
T119	0	34	0	0
T129	0	12	0	0
T131	331782	0	0	0
T132	337937	0	0	0
T133	30022	0	0	0
T134	271133	0	0	0
T135	852	0	0	0
T136	190439	0	0	0
T137	1548	0	0	0
T138	156618	0	0	0
T139	177810	0	0	0
T150	0	47	0	0
T151	0	3	0	0
T152	0	18	0	0
T153	0	16	0	0
T154	0	6	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1489078454	1912	0	0
T50	256154	61	0	0
T106	0	28	0	0
T110	0	22	0	0
T119	0	49	0	0
T129	0	5	0	0
T131	331782	0	0	0
T132	337937	0	0	0
T133	30022	0	0	0
T134	271133	0	0	0
T135	852	0	0	0
T136	190439	0	0	0
T137	1548	0	0	0
T138	156618	0	0	0
T139	177810	0	0	0
T150	0	11	0	0
T151	0	7	0	0
T152	0	30	0	0
T153	0	13	0	0
T154	0	2	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1489078454	2029	0	0
T50	256154	71	0	0
T106	0	30	0	0
T110	0	24	0	0
T119	0	40	0	0
T129	0	9	0	0
T131	331782	0	0	0
T132	337937	0	0	0
T133	30022	0	0	0
T134	271133	0	0	0
T135	852	0	0	0
T136	190439	0	0	0
T137	1548	0	0	0
T138	156618	0	0	0
T139	177810	0	0	0
T150	0	26	0	0
T151	0	3	0	0
T152	0	12	0	0
T153	0	10	0	0
T154	0	6	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1489078454	1876	0	0
T50	256154	62	0	0
T106	0	23	0	0
T110	0	38	0	0
T119	0	35	0	0
T129	0	8	0	0
T131	331782	0	0	0
T132	337937	0	0	0
T133	30022	0	0	0
T134	271133	0	0	0
T135	852	0	0	0
T136	190439	0	0	0
T137	1548	0	0	0
T138	156618	0	0	0
T139	177810	0	0	0
T150	0	56	0	0
T151	0	2	0	0
T152	0	16	0	0
T153	0	25	0	0
T154	0	8	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1489078454	1996	0	0
T50	256154	47	0	0
T106	0	33	0	0
T110	0	23	0	0
T119	0	43	0	0
T129	0	9	0	0
T131	331782	0	0	0
T132	337937	0	0	0
T133	30022	0	0	0
T134	271133	0	0	0
T135	852	0	0	0
T136	190439	0	0	0
T137	1548	0	0	0
T138	156618	0	0	0
T139	177810	0	0	0
T150	0	50	0	0
T151	0	3	0	0
T152	0	17	0	0
T153	0	20	0	0
T154	0	12	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1489078454	1840	0	0
T50	256154	64	0	0
T106	0	39	0	0
T110	0	40	0	0
T119	0	38	0	0
T129	0	8	0	0
T131	331782	0	0	0
T132	337937	0	0	0
T133	30022	0	0	0
T134	271133	0	0	0
T135	852	0	0	0
T136	190439	0	0	0
T137	1548	0	0	0
T138	156618	0	0	0
T139	177810	0	0	0
T150	0	24	0	0
T152	0	17	0	0
T153	0	18	0	0
T154	0	2	0	0
T159	0	408	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1489078454	1904	0	0
T50	256154	78	0	0
T106	0	24	0	0
T110	0	9	0	0
T119	0	45	0	0
T129	0	1	0	0
T131	331782	0	0	0
T132	337937	0	0	0
T133	30022	0	0	0
T134	271133	0	0	0
T135	852	0	0	0
T136	190439	0	0	0
T137	1548	0	0	0
T138	156618	0	0	0
T139	177810	0	0	0
T150	0	23	0	0
T151	0	1	0	0
T152	0	20	0	0
T153	0	14	0	0
T154	0	8	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1489078454	2006	0	0
T50	256154	67	0	0
T106	0	22	0	0
T110	0	15	0	0
T119	0	51	0	0
T129	0	13	0	0
T131	331782	0	0	0
T132	337937	0	0	0
T133	30022	0	0	0
T134	271133	0	0	0
T135	852	0	0	0
T136	190439	0	0	0
T137	1548	0	0	0
T138	156618	0	0	0
T139	177810	0	0	0
T150	0	23	0	0
T152	0	21	0	0
T153	0	11	0	0
T154	0	3	0	0
T159	0	435	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1489078454	1967	0	0
T50	256154	43	0	0
T106	0	31	0	0
T110	0	26	0	0
T119	0	43	0	0
T129	0	9	0	0
T131	331782	0	0	0
T132	337937	0	0	0
T133	30022	0	0	0
T134	271133	0	0	0
T135	852	0	0	0
T136	190439	0	0	0
T137	1548	0	0	0
T138	156618	0	0	0
T139	177810	0	0	0
T150	0	50	0	0
T151	0	3	0	0
T152	0	30	0	0
T153	0	22	0	0
T154	0	5	0	0