Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

165285440

1

T1

19

T2

141912

T3

827

full_word

132839121

1

T1

7

T2

100324

T3

1405

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	298124241	1			T1	26		T2	242236		T3	2232
auto[TlIntgErrCmd]	111	1			T51	5		T108	3		T109	7
auto[TlIntgErrData]	118	1			T51	1		T108	2		T109	6
auto[TlIntgErrBoth]	91	1			T51	4		T108	5		T109	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

156554596

1

T1

1

T2

127311

T3

1159

auto[1]

141569965

1

T1

25

T2

114925

T3

1073

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	99521202	1			T2	845474		T3	445		T4	4557
auto[TlIntgErrNone]	partial	auto[1]	65763940	1			T1	19		T2	573646		T3	382
auto[TlIntgErrNone]	full_word	auto[0]	57033263	1			T1	1		T2	427638		T3	714
auto[TlIntgErrNone]	full_word	auto[1]	75805836	1			T1	6		T2	575610		T3	691
auto[TlIntgErrCmd]	partial	auto[0]	39	1			T51	3		T108	1		T109	3
auto[TlIntgErrCmd]	partial	auto[1]	69	1			T51	2		T108	2		T109	4
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T180	1		T181	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	1	1			T182	1		-	-		-	-
auto[TlIntgErrData]	partial	auto[0]	49	1			T109	2		T176	2		T183	1
auto[TlIntgErrData]	partial	auto[1]	55	1			T51	1		T108	2		T109	2
auto[TlIntgErrData]	full_word	auto[0]	7	1			T182	1		T184	2		T185	1
auto[TlIntgErrData]	full_word	auto[1]	7	1			T109	2		T176	2		T184	1
auto[TlIntgErrBoth]	partial	auto[0]	32	1			T51	1		T108	3		T109	2
auto[TlIntgErrBoth]	partial	auto[1]	54	1			T51	2		T108	2		T109	5
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T51	1		T178	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T186	1		T187	1		T188	1