Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1422270085	32931	0	0
entropy_period_rd_A	1422270085	2084	0	0
intr_enable_rd_A	1422270085	2596	0	0
prefix_0_rd_A	1422270085	1692	0	0
prefix_10_rd_A	1422270085	1768	0	0
prefix_1_rd_A	1422270085	1701	0	0
prefix_2_rd_A	1422270085	1633	0	0
prefix_3_rd_A	1422270085	1660	0	0
prefix_4_rd_A	1422270085	1522	0	0
prefix_5_rd_A	1422270085	1771	0	0
prefix_6_rd_A	1422270085	1625	0	0
prefix_7_rd_A	1422270085	1681	0	0
prefix_8_rd_A	1422270085	1611	0	0
prefix_9_rd_A	1422270085	1653	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1422270085	32931	0	0
T49	297893	29179	0	0
T50	0	155	0	0
T51	0	2	0	0
T106	0	130	0	0
T110	0	292	0	0
T112	0	71	0	0
T130	0	3	0	0
T131	0	7	0	0
T132	0	5	0	0
T133	23514	0	0	0
T134	212851	0	0	0
T135	712472	0	0	0
T136	24542	0	0	0
T137	423335	0	0	0
T138	325758	0	0	0
T139	288603	0	0	0
T140	6300	0	0	0
T141	6367	0	0	0
T142	0	57	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1422270085	2084	0	0
T51	12537	50	0	0
T98	4879	12	0	0
T99	7917	20	0	0
T130	7240	20	0	0
T132	4715	6	0	0
T150	2344	13	0	0
T151	1889	4	0	0
T152	43073	226	0	0
T153	11397	37	0	0
T154	5318	18	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1422270085	2596	0	0
T51	12537	91	0	0
T98	4879	28	0	0
T99	7917	18	0	0
T130	7240	15	0	0
T132	4715	24	0	0
T142	4443	5	0	0
T151	1889	4	0	0
T152	43073	206	0	0
T153	11397	31	0	0
T154	5318	19	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1422270085	1692	0	0
T51	12537	47	0	0
T98	4879	18	0	0
T99	7917	23	0	0
T130	7240	18	0	0
T132	4715	4	0	0
T150	2344	2	0	0
T151	1889	5	0	0
T152	43073	233	0	0
T153	11397	43	0	0
T154	5318	2	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1422270085	1768	0	0
T51	12537	51	0	0
T98	4879	24	0	0
T99	7917	29	0	0
T130	7240	13	0	0
T132	4715	1	0	0
T151	1889	5	0	0
T152	43073	285	0	0
T153	11397	25	0	0
T154	5318	7	0	0
T155	10302	32	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1422270085	1701	0	0
T51	12537	55	0	0
T98	4879	19	0	0
T99	7917	26	0	0
T130	7240	18	0	0
T150	2344	7	0	0
T151	1889	8	0	0
T152	43073	229	0	0
T153	11397	55	0	0
T154	5318	9	0	0
T155	10302	81	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1422270085	1633	0	0
T51	12537	38	0	0
T98	4879	24	0	0
T99	7917	32	0	0
T130	7240	20	0	0
T132	4715	8	0	0
T150	2344	1	0	0
T151	1889	3	0	0
T152	43073	231	0	0
T153	11397	21	0	0
T154	5318	10	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1422270085	1660	0	0
T51	12537	43	0	0
T98	4879	13	0	0
T99	7917	19	0	0
T130	7240	26	0	0
T132	4715	8	0	0
T150	2344	2	0	0
T151	1889	9	0	0
T152	43073	266	0	0
T153	11397	39	0	0
T154	5318	7	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1422270085	1522	0	0
T51	12537	39	0	0
T98	4879	13	0	0
T99	7917	34	0	0
T130	7240	16	0	0
T132	4715	2	0	0
T150	2344	2	0	0
T151	1889	3	0	0
T152	43073	183	0	0
T153	11397	46	0	0
T154	5318	9	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1422270085	1771	0	0
T51	12537	47	0	0
T98	4879	16	0	0
T99	7917	30	0	0
T130	7240	26	0	0
T132	4715	3	0	0
T150	2344	1	0	0
T151	1889	2	0	0
T152	43073	284	0	0
T153	11397	61	0	0
T154	5318	12	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1422270085	1625	0	0
T51	12537	45	0	0
T98	4879	13	0	0
T99	7917	30	0	0
T130	7240	13	0	0
T150	2344	10	0	0
T151	1889	4	0	0
T152	43073	204	0	0
T153	11397	35	0	0
T154	5318	17	0	0
T155	10302	55	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1422270085	1681	0	0
T51	12537	39	0	0
T98	4879	6	0	0
T99	7917	22	0	0
T130	7240	20	0	0
T132	4715	11	0	0
T150	2344	6	0	0
T151	1889	5	0	0
T152	43073	237	0	0
T153	11397	31	0	0
T154	5318	14	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1422270085	1611	0	0
T51	12537	46	0	0
T98	4879	29	0	0
T99	7917	18	0	0
T130	7240	22	0	0
T132	4715	8	0	0
T151	1889	2	0	0
T152	43073	271	0	0
T153	11397	47	0	0
T154	5318	7	0	0
T155	10302	57	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1422270085	1653	0	0
T51	12537	47	0	0
T98	4879	21	0	0
T99	7917	39	0	0
T130	7240	18	0	0
T132	4715	10	0	0
T150	2344	7	0	0
T151	1889	5	0	0
T152	43073	216	0	0
T153	11397	57	0	0
T154	5318	13	0	0