Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

172635388

1

T1

278912

T2

652

T3

398326

full_word

140434301

1

T1

183243

T2

1409

T3

261604

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	313069369	1			T1	462155		T2	2061		T3	659930
auto[TlIntgErrCmd]	100	1			T114	5		T116	3		T117	1
auto[TlIntgErrData]	118	1			T114	3		T116	9		T117	4
auto[TlIntgErrBoth]	102	1			T114	2		T116	8		T117	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

164272000

1

T1

238131

T2

1075

T3

338233

auto[1]

148797689

1

T1

224024

T2

986

T3

321697

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	103773723	1			T1	166708		T2	399		T3	239056
auto[TlIntgErrNone]	partial	auto[1]	68861372	1			T1	112204		T2	253		T3	159270
auto[TlIntgErrNone]	full_word	auto[0]	60498132	1			T1	71423		T2	676		T3	99177
auto[TlIntgErrNone]	full_word	auto[1]	79936142	1			T1	111820		T2	733		T3	162427
auto[TlIntgErrCmd]	partial	auto[0]	40	1			T114	2		T116	1		T185	1
auto[TlIntgErrCmd]	partial	auto[1]	52	1			T114	1		T116	2		T117	1
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T186	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	7	1			T114	2		T183	1		T187	2
auto[TlIntgErrData]	partial	auto[0]	63	1			T114	2		T116	4		T117	3
auto[TlIntgErrData]	partial	auto[1]	46	1			T114	1		T116	4		T117	1
auto[TlIntgErrData]	full_word	auto[0]	5	1			T158	1		T182	1		T188	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T116	1		T186	1		T188	1
auto[TlIntgErrBoth]	partial	auto[0]	35	1			T116	2		T117	2		T159	1
auto[TlIntgErrBoth]	partial	auto[1]	57	1			T114	1		T116	5		T117	3
auto[TlIntgErrBoth]	full_word	auto[0]	1	1			T186	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	9	1			T114	1		T116	1		T123	1