Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1439640326	111491	0	0
entropy_period_rd_A	1439640326	1723	0	0
intr_enable_rd_A	1439640326	2413	0	0
prefix_0_rd_A	1439640326	1721	0	0
prefix_10_rd_A	1439640326	1848	0	0
prefix_1_rd_A	1439640326	1920	0	0
prefix_2_rd_A	1439640326	1786	0	0
prefix_3_rd_A	1439640326	1824	0	0
prefix_4_rd_A	1439640326	1748	0	0
prefix_5_rd_A	1439640326	1821	0	0
prefix_6_rd_A	1439640326	1891	0	0
prefix_7_rd_A	1439640326	1717	0	0
prefix_8_rd_A	1439640326	1743	0	0
prefix_9_rd_A	1439640326	1734	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1439640326	111491	0	0
T33	287848	39342	0	0
T54	0	69353	0	0
T55	0	5	0	0
T116	0	4	0	0
T117	0	1	0	0
T118	0	137	0	0
T119	0	210	0	0
T127	0	3	0	0
T128	0	2	0	0
T130	43171	0	0	0
T131	686404	0	0	0
T132	237959	0	0	0
T133	234747	0	0	0
T134	64890	0	0	0
T135	146262	0	0	0
T136	956255	0	0	0
T137	933373	0	0	0
T138	176236	0	0	0
T139	0	5	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1439640326	1723	0	0
T100	11914	45	0	0
T103	5484	30	0	0
T129	4157	13	0	0
T155	1989	8	0	0
T156	1573	18	0	0
T157	10593	91	0	0
T158	24564	127	0	0
T159	28943	148	0	0
T160	3066	12	0	0
T161	2736	11	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1439640326	2413	0	0
T98	3083	5	0	0
T100	11914	41	0	0
T129	4157	17	0	0
T155	1989	3	0	0
T156	1573	6	0	0
T157	10593	27	0	0
T158	24564	142	0	0
T162	2788	14	0	0
T163	3070	6	0	0
T164	1859	6	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1439640326	1721	0	0
T98	3083	3	0	0
T100	11914	7	0	0
T103	5484	16	0	0
T129	4157	6	0	0
T156	1573	3	0	0
T157	10593	67	0	0
T158	24564	100	0	0
T159	28943	86	0	0
T162	2788	5	0	0
T163	3070	6	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1439640326	1848	0	0
T98	3083	6	0	0
T100	11914	29	0	0
T129	4157	4	0	0
T155	1989	2	0	0
T156	1573	4	0	0
T157	10593	62	0	0
T158	24564	63	0	0
T162	2788	2	0	0
T163	3070	3	0	0
T164	1859	7	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1439640326	1920	0	0
T98	3083	2	0	0
T100	11914	30	0	0
T129	4157	11	0	0
T155	1989	7	0	0
T156	1573	3	0	0
T157	10593	13	0	0
T158	24564	58	0	0
T159	28943	94	0	0
T162	2788	7	0	0
T163	3070	6	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1439640326	1786	0	0
T98	3083	5	0	0
T100	11914	28	0	0
T129	4157	8	0	0
T155	1989	5	0	0
T156	1573	4	0	0
T157	10593	16	0	0
T158	24564	92	0	0
T162	2788	3	0	0
T163	3070	2	0	0
T164	1859	2	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1439640326	1824	0	0
T98	3083	4	0	0
T100	11914	28	0	0
T103	5484	19	0	0
T129	4157	8	0	0
T157	10593	45	0	0
T158	24564	71	0	0
T159	28943	90	0	0
T162	2788	3	0	0
T163	3070	1	0	0
T164	1859	5	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1439640326	1748	0	0
T98	3083	10	0	0
T100	11914	33	0	0
T103	5484	30	0	0
T129	4157	4	0	0
T155	1989	6	0	0
T156	1573	1	0	0
T157	10593	20	0	0
T158	24564	87	0	0
T159	28943	108	0	0
T163	3070	8	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1439640326	1821	0	0
T98	3083	1	0	0
T100	11914	56	0	0
T129	4157	4	0	0
T155	1989	1	0	0
T156	1573	2	0	0
T157	10593	42	0	0
T158	24564	95	0	0
T162	2788	5	0	0
T163	3070	4	0	0
T164	1859	9	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1439640326	1891	0	0
T98	3083	2	0	0
T100	11914	21	0	0
T155	1989	4	0	0
T156	1573	1	0	0
T157	10593	69	0	0
T158	24564	74	0	0
T159	28943	95	0	0
T162	2788	4	0	0
T163	3070	7	0	0
T164	1859	2	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1439640326	1717	0	0
T98	3083	4	0	0
T100	11914	32	0	0
T103	5484	19	0	0
T155	1989	6	0	0
T157	10593	53	0	0
T158	24564	74	0	0
T159	28943	71	0	0
T160	3066	7	0	0
T161	2736	12	0	0
T164	1859	9	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1439640326	1743	0	0
T98	3083	8	0	0
T100	11914	30	0	0
T129	4157	3	0	0
T155	1989	2	0	0
T156	1573	6	0	0
T157	10593	44	0	0
T158	24564	79	0	0
T162	2788	2	0	0
T163	3070	2	0	0
T164	1859	1	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1439640326	1734	0	0
T98	3083	4	0	0
T100	11914	36	0	0
T129	4157	5	0	0
T155	1989	3	0	0
T156	1573	3	0	0
T157	10593	25	0	0
T158	24564	99	0	0
T159	28943	64	0	0
T162	2788	2	0	0
T163	3070	1	0	0