Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

172521925

1

T1

6309

T2

55535

T3

426965

full_word

139369646

1

T1

12451

T2

101641

T3

300246

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	311891231	1			T1	18760		T2	157176		T3	727211
auto[TlIntgErrCmd]	109	1			T112	6		T113	7		T114	6
auto[TlIntgErrData]	108	1			T112	5		T113	4		T114	5
auto[TlIntgErrBoth]	123	1			T112	9		T113	9		T114	9

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

163361951

1

T1

13178

T2

108509

T3

385328

auto[1]

148529620

1

T1

5582

T2

48667

T3

341883

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	103326211	1			T1	3743		T2	33977		T3	257350
auto[TlIntgErrNone]	partial	auto[1]	69195397	1			T1	2566		T2	21558		T3	169615
auto[TlIntgErrNone]	full_word	auto[0]	60035584	1			T1	9435		T2	74532		T3	127978
auto[TlIntgErrNone]	full_word	auto[1]	79334039	1			T1	3016		T2	27109		T3	172268
auto[TlIntgErrCmd]	partial	auto[0]	46	1			T112	2		T113	2		T114	1
auto[TlIntgErrCmd]	partial	auto[1]	56	1			T112	4		T113	4		T114	5
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T113	1		T165	1		T166	2
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T135	1		T167	1		T168	1
auto[TlIntgErrData]	partial	auto[0]	45	1			T112	3		T113	3		T114	2
auto[TlIntgErrData]	partial	auto[1]	53	1			T112	2		T114	2		T135	2
auto[TlIntgErrData]	full_word	auto[0]	6	1			T113	1		T169	1		T165	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T114	1		T135	1		T136	1
auto[TlIntgErrBoth]	partial	auto[0]	50	1			T112	3		T113	3		T114	1
auto[TlIntgErrBoth]	partial	auto[1]	67	1			T112	6		T113	4		T114	8
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T113	1		T135	1		T170	1
auto[TlIntgErrBoth]	full_word	auto[1]	1	1			T113	1		-	-		-	-