Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1470144381	219695	0	0
entropy_period_rd_A	1470144381	1341	0	0
intr_enable_rd_A	1470144381	1805	0	0
prefix_0_rd_A	1470144381	1272	0	0
prefix_10_rd_A	1470144381	1138	0	0
prefix_1_rd_A	1470144381	1211	0	0
prefix_2_rd_A	1470144381	1155	0	0
prefix_3_rd_A	1470144381	1254	0	0
prefix_4_rd_A	1470144381	1050	0	0
prefix_5_rd_A	1470144381	1136	0	0
prefix_6_rd_A	1470144381	1184	0	0
prefix_7_rd_A	1470144381	1199	0	0
prefix_8_rd_A	1470144381	1339	0	0
prefix_9_rd_A	1470144381	1163	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1470144381	219695	0	0
T5	2920	0	0	0
T6	5010	0	0	0
T16	593622	73918	0	0
T17	24677	0	0	0
T18	7160	0	0	0
T19	132915	0	0	0
T23	213341	0	0	0
T45	1330	0	0	0
T48	0	10048	0	0
T49	0	68793	0	0
T87	597968	0	0	0
T89	0	63335	0	0
T96	38902	0	0	0
T112	0	1	0	0
T113	0	2	0	0
T114	0	2	0	0
T118	0	61	0	0
T119	0	291	0	0
T120	0	126	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1470144381	1341	0	0
T113	25202	51	0	0
T133	2683	8	0	0
T134	9970	66	0	0
T135	11610	52	0	0
T136	13431	52	0	0
T137	4832	5	0	0
T138	45293	238	0	0
T139	4226	18	0	0
T140	3396	8	0	0
T141	3232	4	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1470144381	1805	0	0
T113	25202	93	0	0
T133	2683	22	0	0
T134	9970	53	0	0
T135	11610	69	0	0
T136	13431	86	0	0
T137	4832	31	0	0
T138	45293	219	0	0
T139	4226	16	0	0
T142	1173	16	0	0
T143	1416	14	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1470144381	1272	0	0
T113	25202	46	0	0
T133	2683	8	0	0
T134	9970	29	0	0
T135	11610	36	0	0
T136	13431	37	0	0
T138	45293	256	0	0
T139	4226	10	0	0
T140	3396	10	0	0
T141	3232	11	0	0
T144	6304	38	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1470144381	1138	0	0
T113	25202	50	0	0
T133	2683	5	0	0
T134	9970	22	0	0
T135	11610	31	0	0
T136	13431	39	0	0
T137	4832	13	0	0
T138	45293	220	0	0
T139	4226	6	0	0
T140	3396	2	0	0
T141	3232	3	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1470144381	1211	0	0
T108	3055	9	0	0
T113	25202	58	0	0
T133	2683	8	0	0
T134	9970	53	0	0
T135	11610	51	0	0
T136	13431	32	0	0
T137	4832	20	0	0
T138	45293	207	0	0
T139	4226	4	0	0
T140	3396	7	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1470144381	1155	0	0
T108	3055	7	0	0
T113	25202	51	0	0
T133	2683	7	0	0
T134	9970	26	0	0
T135	11610	31	0	0
T136	13431	50	0	0
T137	4832	4	0	0
T138	45293	208	0	0
T139	4226	10	0	0
T140	3396	9	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1470144381	1254	0	0
T113	25202	35	0	0
T133	2683	13	0	0
T134	9970	49	0	0
T135	11610	32	0	0
T136	13431	38	0	0
T137	4832	19	0	0
T138	45293	293	0	0
T139	4226	2	0	0
T140	3396	1	0	0
T141	3232	1	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1470144381	1050	0	0
T108	3055	3	0	0
T113	25202	23	0	0
T133	2683	5	0	0
T134	9970	14	0	0
T135	11610	43	0	0
T136	13431	40	0	0
T138	45293	251	0	0
T139	4226	9	0	0
T140	3396	12	0	0
T145	1637	7	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1470144381	1136	0	0
T108	3055	2	0	0
T113	25202	32	0	0
T133	2683	6	0	0
T134	9970	64	0	0
T135	11610	47	0	0
T136	13431	43	0	0
T137	4832	31	0	0
T138	45293	220	0	0
T139	4226	5	0	0
T140	3396	6	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1470144381	1184	0	0
T113	25202	56	0	0
T133	2683	6	0	0
T134	9970	30	0	0
T135	11610	58	0	0
T136	13431	49	0	0
T137	4832	9	0	0
T138	45293	257	0	0
T139	4226	10	0	0
T140	3396	7	0	0
T141	3232	15	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1470144381	1199	0	0
T113	25202	28	0	0
T133	2683	5	0	0
T134	9970	22	0	0
T135	11610	34	0	0
T136	13431	52	0	0
T137	4832	19	0	0
T138	45293	215	0	0
T139	4226	7	0	0
T140	3396	10	0	0
T141	3232	8	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1470144381	1339	0	0
T113	25202	31	0	0
T133	2683	14	0	0
T134	9970	67	0	0
T135	11610	43	0	0
T136	13431	37	0	0
T137	4832	4	0	0
T138	45293	231	0	0
T139	4226	1	0	0
T140	3396	3	0	0
T141	3232	4	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1470144381	1163	0	0
T113	25202	33	0	0
T133	2683	11	0	0
T134	9970	41	0	0
T135	11610	42	0	0
T136	13431	46	0	0
T137	4832	12	0	0
T138	45293	255	0	0
T139	4226	5	0	0
T140	3396	7	0	0
T141	3232	1	0	0