Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	173161842	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

141123223

1

T1

86303

T2

261523

T3

76197

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	165223180	1			T1	108853		T2	337059		T3	81596
values[0x0]	71706398	1			T1	45928		T2	154471		T3	19357
values[0x1]	77355487	1			T1	49888		T2	166069		T3	21023

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	134951209	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

179333856

1

T1

112235

T2

347887

T3

86510

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	966762	1			T1	670		T3	468		T14	1683
valid_sources[0x01]	961822	1			T1	1024		T3	485		T14	1733
valid_sources[0x02]	3367469	1			T1	786		T3	538		T14	1737
valid_sources[0x03]	1030075	1			T1	767		T3	472		T14	1766
valid_sources[0x04]	966511	1			T1	739		T3	440		T14	1716
valid_sources[0x05]	963620	1			T1	708		T3	476		T14	1777
valid_sources[0x06]	965185	1			T1	761		T3	459		T14	1821
valid_sources[0x07]	967576	1			T1	765		T3	492		T14	1729
valid_sources[0x08]	957760	1			T1	717		T3	507		T14	1760
valid_sources[0x09]	961678	1			T1	828		T3	449		T14	1814
valid_sources[0x0a]	1041174	1			T1	761		T3	452		T14	1791
valid_sources[0x0b]	958093	1			T1	833		T3	491		T14	1672
valid_sources[0x0c]	960614	1			T1	791		T3	483		T14	1770
valid_sources[0x0d]	1850107	1			T1	568		T3	462		T14	1817
valid_sources[0x0e]	965011	1			T1	852		T3	477		T14	1686
valid_sources[0x0f]	959144	1			T1	952		T3	498		T14	1734
valid_sources[0x10]	1730134	1			T1	666		T3	489		T14	1763
valid_sources[0x11]	962693	1			T1	1040		T3	446		T14	1706
valid_sources[0x12]	2986501	1			T1	862		T3	479		T14	1784
valid_sources[0x13]	1037946	1			T1	545		T3	499		T14	1752
valid_sources[0x14]	962600	1			T1	957		T3	472		T14	1687
valid_sources[0x15]	974621	1			T1	699		T3	474		T14	1770
valid_sources[0x16]	961024	1			T1	766		T3	483		T14	1744
valid_sources[0x17]	1012806	1			T1	657		T3	475		T14	1733
valid_sources[0x18]	1802463	1			T1	786		T3	467		T14	1890
valid_sources[0x19]	961735	1			T1	732		T3	509		T14	1858
valid_sources[0x1a]	981979	1			T1	738		T3	492		T14	1689
valid_sources[0x1b]	1884640	1			T1	766		T3	500		T14	1765
valid_sources[0x1c]	1031400	1			T1	745		T3	460		T14	1687
valid_sources[0x1d]	958088	1			T1	784		T3	504		T14	1742
valid_sources[0x1e]	966344	1			T1	681		T3	418		T14	1789
valid_sources[0x1f]	961853	1			T1	819		T3	485		T14	1810
valid_sources[0x20]	961412	1			T1	868		T3	480		T14	1780
valid_sources[0x21]	2985079	1			T1	791		T3	485		T14	1734
valid_sources[0x22]	1104686	1			T1	943		T3	493		T14	1815
valid_sources[0x23]	961660	1			T1	442		T3	455		T14	1722
valid_sources[0x24]	958448	1			T1	849		T3	503		T14	1715
valid_sources[0x25]	967815	1			T1	745		T3	493		T14	1763
valid_sources[0x26]	1428151	1			T1	761		T3	483		T14	1717
valid_sources[0x27]	961538	1			T1	823		T3	440		T14	1733
valid_sources[0x28]	959528	1			T1	995		T3	465		T14	1853
valid_sources[0x29]	960546	1			T1	909		T3	523		T14	1769
valid_sources[0x2a]	1051037	1			T1	969		T3	477		T14	1769
valid_sources[0x2b]	1027708	1			T1	896		T3	483		T14	1806
valid_sources[0x2c]	958992	1			T1	890		T3	494		T14	1793
valid_sources[0x2d]	996069	1			T1	895		T3	455		T14	1710
valid_sources[0x2e]	959589	1			T1	874		T3	415		T14	1783
valid_sources[0x2f]	1875447	1			T1	739		T3	477		T14	1714
valid_sources[0x30]	1007274	1			T1	778		T3	487		T14	1821
valid_sources[0x31]	964674	1			T1	877		T3	521		T14	1751
valid_sources[0x32]	956557	1			T1	962		T3	476		T14	1779
valid_sources[0x33]	1311058	1			T1	847		T3	467		T14	1745
valid_sources[0x34]	3012865	1			T1	806		T3	482		T14	1749
valid_sources[0x35]	1667001	1			T1	639		T2	657599		T3	492
valid_sources[0x36]	960312	1			T1	901		T3	497		T14	1746
valid_sources[0x37]	959049	1			T1	829		T3	491		T14	1800
valid_sources[0x38]	959869	1			T1	693		T3	565		T14	1781
valid_sources[0x39]	964221	1			T1	758		T3	488		T14	1832
valid_sources[0x3a]	960000	1			T1	598		T3	444		T14	1789
valid_sources[0x3b]	1367632	1			T1	812		T3	458		T14	1787
valid_sources[0x3c]	1408344	1			T1	1121		T3	495		T14	1787
valid_sources[0x3d]	969161	1			T1	827		T3	458		T14	1728
valid_sources[0x3e]	960771	1			T1	738		T3	475		T14	1759
valid_sources[0x3f]	958992	1			T1	823		T3	465		T14	1678
valid_sources[0x40]	1845668	1			T1	758		T3	512		T14	1702
valid_sources[0x41]	962703	1			T1	880		T3	509		T14	1660
valid_sources[0x42]	965179	1			T1	625		T3	419		T14	1779
valid_sources[0x43]	1416578	1			T1	655		T3	463		T14	1718
valid_sources[0x44]	964152	1			T1	686		T3	452		T14	1804
valid_sources[0x45]	964003	1			T1	774		T3	464		T14	1783
valid_sources[0x46]	954442	1			T1	723		T3	455		T14	1747
valid_sources[0x47]	957311	1			T1	888		T3	500		T14	1743
valid_sources[0x48]	960237	1			T1	728		T3	487		T14	1752
valid_sources[0x49]	960189	1			T1	1004		T3	486		T14	1761
valid_sources[0x4a]	955864	1			T1	827		T3	457		T14	1770
valid_sources[0x4b]	1410562	1			T1	746		T3	451		T14	1724
valid_sources[0x4c]	961485	1			T1	924		T3	469		T14	1729
valid_sources[0x4d]	2801521	1			T1	851		T3	482		T14	1742
valid_sources[0x4e]	954667	1			T1	732		T3	457		T14	1721
valid_sources[0x4f]	3403132	1			T1	920		T3	471		T14	1763
valid_sources[0x50]	960822	1			T1	823		T3	450		T14	1760
valid_sources[0x51]	1126440	1			T1	634		T3	450		T14	1679
valid_sources[0x52]	1802165	1			T1	854		T3	484		T14	1727
valid_sources[0x53]	1034793	1			T1	654		T3	478		T14	1754
valid_sources[0x54]	1085240	1			T1	733		T3	486		T14	1778
valid_sources[0x55]	972739	1			T1	798		T3	488		T14	1726
valid_sources[0x56]	1282722	1			T1	743		T3	435		T14	1760
valid_sources[0x57]	1065052	1			T1	805		T3	474		T14	1784
valid_sources[0x58]	1237967	1			T1	840		T3	469		T14	1694
valid_sources[0x59]	961132	1			T1	827		T3	538		T14	1805
valid_sources[0x5a]	1419916	1			T1	811		T3	464		T14	1755
valid_sources[0x5b]	959388	1			T1	670		T3	518		T14	1807
valid_sources[0x5c]	960200	1			T1	688		T3	460		T14	1750
valid_sources[0x5d]	1630402	1			T1	843		T3	466		T14	1790
valid_sources[0x5e]	961415	1			T1	622		T3	495		T14	1792
valid_sources[0x5f]	1109681	1			T1	771		T3	482		T14	1728
valid_sources[0x60]	977907	1			T1	879		T3	437		T14	1767
valid_sources[0x61]	1773824	1			T1	839		T3	460		T14	1841
valid_sources[0x62]	954456	1			T1	988		T3	491		T14	1805
valid_sources[0x63]	962049	1			T1	768		T3	445		T14	1762
valid_sources[0x64]	2001684	1			T1	881		T3	474		T14	1715
valid_sources[0x65]	963009	1			T1	919		T3	467		T14	1814
valid_sources[0x66]	961572	1			T1	798		T3	452		T14	1738
valid_sources[0x67]	1043003	1			T1	766		T3	500		T14	1741
valid_sources[0x68]	960246	1			T1	712		T3	456		T14	1689
valid_sources[0x69]	961966	1			T1	838		T3	516		T14	1791
valid_sources[0x6a]	960586	1			T1	834		T3	462		T14	1685
valid_sources[0x6b]	973016	1			T1	673		T3	481		T14	1805
valid_sources[0x6c]	1622914	1			T1	829		T3	481		T14	1751
valid_sources[0x6d]	3407952	1			T1	868		T3	453		T14	1795
valid_sources[0x6e]	959292	1			T1	533		T3	452		T14	1755
valid_sources[0x6f]	3362310	1			T1	933		T3	497		T14	1682
valid_sources[0x70]	1004424	1			T1	1032		T3	440		T14	1701
valid_sources[0x71]	967669	1			T1	1018		T3	495		T14	1806
valid_sources[0x72]	970456	1			T1	903		T3	442		T14	1720
valid_sources[0x73]	989862	1			T1	754		T3	475		T14	1748
valid_sources[0x74]	961366	1			T1	715		T3	498		T14	1734
valid_sources[0x75]	958440	1			T1	1033		T3	443		T14	1761
valid_sources[0x76]	2064968	1			T1	801		T3	458		T14	1800
valid_sources[0x77]	960573	1			T1	549		T3	469		T14	1804
valid_sources[0x78]	962400	1			T1	768		T3	468		T14	1748
valid_sources[0x79]	965668	1			T1	688		T3	502		T14	1704
valid_sources[0x7a]	1000720	1			T1	900		T3	493		T14	1782
valid_sources[0x7b]	996212	1			T1	833		T3	505		T14	1702
valid_sources[0x7c]	969036	1			T1	791		T3	494		T14	1799
valid_sources[0x7d]	960567	1			T1	757		T3	502		T14	1843
valid_sources[0x7e]	1224119	1			T1	873		T3	482		T14	1789
valid_sources[0x7f]	1807912	1			T1	541		T3	459		T14	1747
valid_sources[0x80]	959251	1			T1	757		T3	466		T14	1863

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

61044568

1

T1

36544

T2

98925

T3

54358

values[0x0]

all_enables

biggest_size

42945910

1

T1

26794

T2

88124

T3

11612

values[0x1]

all_enables

biggest_size

37132745

1

T1

22965

T2

74474

T3

10227