Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

173857149

1

T1

118366

T2

396076

T3

45779

full_word

141166624

1

T1

86303

T2

261523

T3

76197

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	315023483	1			T1	204669		T2	657599		T3	121976
auto[TlIntgErrCmd]	96	1			T118	1		T119	3		T120	4
auto[TlIntgErrData]	93	1			T118	6		T119	4		T120	7
auto[TlIntgErrBoth]	101	1			T118	3		T119	3		T120	9

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

165386410

1

T1

108853

T2

337059

T3

81596

auto[1]

149637363

1

T1

95816

T2

320540

T3

40380

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	104329376	1			T1	72309		T2	238134		T3	27238
auto[TlIntgErrNone]	partial	auto[1]	69527508	1			T1	46057		T2	157942		T3	18541
auto[TlIntgErrNone]	full_word	auto[0]	61056897	1			T1	36544		T2	98925		T3	54358
auto[TlIntgErrNone]	full_word	auto[1]	80109702	1			T1	49759		T2	162598		T3	21839
auto[TlIntgErrCmd]	partial	auto[0]	38	1			T118	1		T120	1		T128	3
auto[TlIntgErrCmd]	partial	auto[1]	50	1			T119	3		T120	2		T128	4
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T128	1		T200	1		T203	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T120	1		T128	1		T137	1
auto[TlIntgErrData]	partial	auto[0]	43	1			T118	2		T119	3		T120	1
auto[TlIntgErrData]	partial	auto[1]	41	1			T118	4		T119	1		T120	6
auto[TlIntgErrData]	full_word	auto[0]	3	1			T128	1		T137	1		T199	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T200	1		T201	1		T203	1
auto[TlIntgErrBoth]	partial	auto[0]	47	1			T118	1		T119	2		T120	2
auto[TlIntgErrBoth]	partial	auto[1]	46	1			T118	1		T120	5		T128	5
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T119	1		T203	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T118	1		T120	2		T128	1