Unified Coverage Report :: Module :: sha3pad_assert_if

Module : sha3pad_assert_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_cov_0/sha3pad_assert_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sha3pad_assert_cov_if	100.00						100.00

---

Module Instance : tb.dut.sha3pad_assert_cov_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sha3pad_assert_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ProcessToRun_A	1500842167	217215	0	0
RunThenComplete_M	1500842167	2264825	0	0

ProcessToRun_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1500842167	217215	0	0
T1	417838	31	0	0
T2	134487	310	0	0
T3	127237	109	0	0
T13	176374	374	0	0
T14	317593	246	0	0
T15	295574	128	0	0
T16	34204	3	0	0
T17	120172	15	0	0
T18	176807	374	0	0
T19	25617	3	0	0

RunThenComplete_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1500842167	2264825	0	0
T1	417838	1154	0	0
T2	134487	5462	0	0
T3	127237	591	0	0
T13	176374	5526	0	0
T14	317593	5427	0	0
T15	295574	689	0	0
T16	34204	18	0	0
T17	120172	77	0	0
T18	176807	5526	0	0
T19	25617	14	0	0