Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1502301945	124394	0	0
entropy_period_rd_A	1502301945	2192	0	0
intr_enable_rd_A	1502301945	3146	0	0
prefix_0_rd_A	1502301945	2510	0	0
prefix_10_rd_A	1502301945	2420	0	0
prefix_1_rd_A	1502301945	2525	0	0
prefix_2_rd_A	1502301945	2521	0	0
prefix_3_rd_A	1502301945	2509	0	0
prefix_4_rd_A	1502301945	2407	0	0
prefix_5_rd_A	1502301945	2386	0	0
prefix_6_rd_A	1502301945	2418	0	0
prefix_7_rd_A	1502301945	2510	0	0
prefix_8_rd_A	1502301945	2436	0	0
prefix_9_rd_A	1502301945	2446	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1502301945	124394	0	0
T35	571703	38002	0	0
T37	0	18653	0	0
T64	0	19961	0	0
T66	2339	0	0	0
T118	0	2	0	0
T119	0	3	0	0
T120	0	4	0	0
T124	0	45057	0	0
T125	0	169	0	0
T126	0	2	0	0
T127	0	2	0	0
T129	61662	0	0	0
T130	485038	0	0	0
T131	462910	0	0	0
T132	55030	0	0	0
T133	664369	0	0	0
T134	128929	0	0	0
T135	604971	0	0	0
T136	302976	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1502301945	2192	0	0
T64	249487	38	0	0
T153	0	6	0	0
T154	0	8	0	0
T155	0	236	0	0
T156	0	12	0	0
T157	0	110	0	0
T158	0	13	0	0
T159	0	6	0	0
T160	0	33	0	0
T161	0	6	0	0
T162	693897	0	0	0
T163	476091	0	0	0
T164	199454	0	0	0
T165	1038	0	0	0
T166	1677	0	0	0
T167	888978	0	0	0
T168	222058	0	0	0
T169	458006	0	0	0
T170	152836	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1502301945	3146	0	0
T64	249487	51	0	0
T115	0	4	0	0
T121	0	10	0	0
T153	0	12	0	0
T155	0	412	0	0
T156	0	6	0	0
T157	0	203	0	0
T162	693897	0	0	0
T163	476091	0	0	0
T164	199454	0	0	0
T165	1038	0	0	0
T166	1677	0	0	0
T167	888978	0	0	0
T168	222058	0	0	0
T169	458006	0	0	0
T170	152836	0	0	0
T171	0	12	0	0
T172	0	39	0	0
T173	0	12	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1502301945	2510	0	0
T64	249487	62	0	0
T115	0	2	0	0
T153	0	3	0	0
T155	0	431	0	0
T157	0	185	0	0
T158	0	1	0	0
T160	0	20	0	0
T161	0	3	0	0
T162	693897	0	0	0
T163	476091	0	0	0
T164	199454	0	0	0
T165	1038	0	0	0
T166	1677	0	0	0
T167	888978	0	0	0
T168	222058	0	0	0
T169	458006	0	0	0
T170	152836	0	0	0
T174	0	300	0	0
T175	0	17	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1502301945	2420	0	0
T64	249487	78	0	0
T115	0	8	0	0
T153	0	1	0	0
T154	0	5	0	0
T155	0	503	0	0
T156	0	7	0	0
T157	0	227	0	0
T158	0	7	0	0
T159	0	8	0	0
T161	0	7	0	0
T162	693897	0	0	0
T163	476091	0	0	0
T164	199454	0	0	0
T165	1038	0	0	0
T166	1677	0	0	0
T167	888978	0	0	0
T168	222058	0	0	0
T169	458006	0	0	0
T170	152836	0	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1502301945	2525	0	0
T64	249487	88	0	0
T115	0	6	0	0
T154	0	7	0	0
T155	0	484	0	0
T156	0	6	0	0
T157	0	213	0	0
T159	0	2	0	0
T160	0	25	0	0
T161	0	1	0	0
T162	693897	0	0	0
T163	476091	0	0	0
T164	199454	0	0	0
T165	1038	0	0	0
T166	1677	0	0	0
T167	888978	0	0	0
T168	222058	0	0	0
T169	458006	0	0	0
T170	152836	0	0	0
T174	0	305	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1502301945	2521	0	0
T64	249487	43	0	0
T153	0	6	0	0
T154	0	13	0	0
T155	0	441	0	0
T156	0	2	0	0
T157	0	271	0	0
T158	0	2	0	0
T159	0	7	0	0
T160	0	27	0	0
T161	0	3	0	0
T162	693897	0	0	0
T163	476091	0	0	0
T164	199454	0	0	0
T165	1038	0	0	0
T166	1677	0	0	0
T167	888978	0	0	0
T168	222058	0	0	0
T169	458006	0	0	0
T170	152836	0	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1502301945	2509	0	0
T64	249487	46	0	0
T115	0	1	0	0
T153	0	4	0	0
T155	0	446	0	0
T156	0	3	0	0
T157	0	234	0	0
T158	0	4	0	0
T159	0	1	0	0
T160	0	14	0	0
T161	0	4	0	0
T162	693897	0	0	0
T163	476091	0	0	0
T164	199454	0	0	0
T165	1038	0	0	0
T166	1677	0	0	0
T167	888978	0	0	0
T168	222058	0	0	0
T169	458006	0	0	0
T170	152836	0	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1502301945	2407	0	0
T64	249487	50	0	0
T115	0	8	0	0
T153	0	2	0	0
T154	0	4	0	0
T155	0	469	0	0
T156	0	1	0	0
T157	0	237	0	0
T158	0	5	0	0
T160	0	23	0	0
T161	0	1	0	0
T162	693897	0	0	0
T163	476091	0	0	0
T164	199454	0	0	0
T165	1038	0	0	0
T166	1677	0	0	0
T167	888978	0	0	0
T168	222058	0	0	0
T169	458006	0	0	0
T170	152836	0	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1502301945	2386	0	0
T64	249487	46	0	0
T115	0	9	0	0
T125	0	3	0	0
T153	0	2	0	0
T154	0	2	0	0
T155	0	434	0	0
T156	0	3	0	0
T157	0	268	0	0
T158	0	4	0	0
T159	0	8	0	0
T162	693897	0	0	0
T163	476091	0	0	0
T164	199454	0	0	0
T165	1038	0	0	0
T166	1677	0	0	0
T167	888978	0	0	0
T168	222058	0	0	0
T169	458006	0	0	0
T170	152836	0	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1502301945	2418	0	0
T64	249487	60	0	0
T115	0	1	0	0
T153	0	9	0	0
T154	0	4	0	0
T155	0	439	0	0
T156	0	9	0	0
T157	0	223	0	0
T158	0	5	0	0
T159	0	1	0	0
T160	0	12	0	0
T162	693897	0	0	0
T163	476091	0	0	0
T164	199454	0	0	0
T165	1038	0	0	0
T166	1677	0	0	0
T167	888978	0	0	0
T168	222058	0	0	0
T169	458006	0	0	0
T170	152836	0	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1502301945	2510	0	0
T64	249487	78	0	0
T115	0	4	0	0
T153	0	1	0	0
T154	0	5	0	0
T155	0	453	0	0
T156	0	10	0	0
T157	0	212	0	0
T158	0	7	0	0
T159	0	5	0	0
T160	0	14	0	0
T162	693897	0	0	0
T163	476091	0	0	0
T164	199454	0	0	0
T165	1038	0	0	0
T166	1677	0	0	0
T167	888978	0	0	0
T168	222058	0	0	0
T169	458006	0	0	0
T170	152836	0	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1502301945	2436	0	0
T64	249487	59	0	0
T115	0	5	0	0
T153	0	6	0	0
T154	0	3	0	0
T155	0	482	0	0
T157	0	213	0	0
T158	0	2	0	0
T159	0	15	0	0
T160	0	28	0	0
T161	0	4	0	0
T162	693897	0	0	0
T163	476091	0	0	0
T164	199454	0	0	0
T165	1038	0	0	0
T166	1677	0	0	0
T167	888978	0	0	0
T168	222058	0	0	0
T169	458006	0	0	0
T170	152836	0	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1502301945	2446	0	0
T64	249487	105	0	0
T115	0	4	0	0
T153	0	9	0	0
T154	0	19	0	0
T155	0	452	0	0
T156	0	2	0	0
T157	0	197	0	0
T158	0	4	0	0
T159	0	9	0	0
T160	0	25	0	0
T162	693897	0	0	0
T163	476091	0	0	0
T164	199454	0	0	0
T165	1038	0	0	0
T166	1677	0	0	0
T167	888978	0	0	0
T168	222058	0	0	0
T169	458006	0	0	0
T170	152836	0	0	0