Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

169693977

1

T1

1198

T2

48134

T3

566

full_word

138828810

1

T1

1947

T2

86422

T3

1405

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	308522477	1			T1	3145		T2	134556		T3	1971
auto[TlIntgErrCmd]	101	1			T104	7		T105	9		T106	8
auto[TlIntgErrData]	96	1			T104	6		T105	4		T106	6
auto[TlIntgErrBoth]	113	1			T104	7		T105	7		T106	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

161895021

1

T1

2207

T2

96080

T3

1029

auto[1]

146627766

1

T1

938

T2

38476

T3

942

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	102012321	1			T1	780		T2	30722		T3	355
auto[TlIntgErrNone]	partial	auto[1]	67681374	1			T1	418		T2	17412		T3	211
auto[TlIntgErrNone]	full_word	auto[0]	59882559	1			T1	1427		T2	65358		T3	674
auto[TlIntgErrNone]	full_word	auto[1]	78946223	1			T1	520		T2	21064		T3	731
auto[TlIntgErrCmd]	partial	auto[0]	45	1			T104	5		T105	4		T106	4
auto[TlIntgErrCmd]	partial	auto[1]	46	1			T104	1		T105	2		T106	4
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T105	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	9	1			T104	1		T105	2		T171	1
auto[TlIntgErrData]	partial	auto[0]	44	1			T104	2		T105	3		T106	4
auto[TlIntgErrData]	partial	auto[1]	42	1			T104	3		T105	1		T106	2
auto[TlIntgErrData]	full_word	auto[0]	5	1			T167	3		T172	1		T173	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T104	1		T170	1		T173	1
auto[TlIntgErrBoth]	partial	auto[0]	43	1			T104	4		T105	3		T106	4
auto[TlIntgErrBoth]	partial	auto[1]	62	1			T104	2		T105	3		T106	2
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T174	1		T169	1		T175	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T104	1		T105	1		T168	1