Unified Coverage Report :: Module :: sha3pad_assert_if

Module : sha3pad_assert_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_cov_0/sha3pad_assert_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sha3pad_assert_cov_if	100.00						100.00

---

Module Instance : tb.dut.sha3pad_assert_cov_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sha3pad_assert_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ProcessToRun_A	1483890336	208193	0	0
RunThenComplete_M	1483890336	2247158	0	0

ProcessToRun_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1483890336	208193	0	0
T1	7879	3	0	0
T2	496457	191	0	0
T3	6670	9	0	0
T12	725361	83	0	0
T13	536958	198	0	0
T14	648743	390	0	0
T15	945150	129	0	0
T16	142370	110	0	0
T17	167837	181	0	0
T18	126030	114	0	0

RunThenComplete_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1483890336	2247158	0	0
T1	7879	13	0	0
T2	496457	897	0	0
T3	6670	31	0	0
T12	725361	361	0	0
T13	536958	1011	0	0
T14	648743	5542	0	0
T15	945150	686	0	0
T16	142370	4022	0	0
T17	167837	958	0	0
T18	126030	605	0	0