Unified Coverage Report :: Module :: prim_packer

Module : prim_packer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.50	100.00	100.00			90.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_msgfifo.u_packer	97.50	100.00	100.00			90.00	100.00

---

Module Instance : tb.dut.u_msgfifo.u_packer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.50	100.00	100.00			90.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.50	100.00	100.00			90.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.92	100.00			100.00	91.67	100.00	u_msgfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_packer

	Line No.	Total	Covered	Percent
TOTAL		66	66	100.00
ALWAYS	65	3	3	100.00
CONT_ASSIGN	72	1	1	100.00
ALWAYS	78	6	6	100.00
ALWAYS	90	5	5	100.00
ALWAYS	157	4	4	100.00
CONT_ASSIGN	165	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	170	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	174	1	1	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	178	1	1	100.00
CONT_ASSIGN	180	1	1	100.00
ALWAYS	185	9	9	100.00
ALWAYS	214	8	8	100.00
ALWAYS	235	3	3	100.00
ALWAYS	243	14	14	100.00
CONT_ASSIGN	279	1	1	100.00
CONT_ASSIGN	283	1	1	100.00
CONT_ASSIGN	291	0	0
CONT_ASSIGN	294	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	296	1	1	100.00
CONT_ASSIGN	299	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
66	1	1
67	1	1
72	1	1
78	1	1
80	1	1
81	1	1
82	1	1
83	1	1
84	1	1
90	1	1
91	1	1
92	1	1
93	1	1
95	1	1
157	1	1
158	1	1
159	1	1
160	1	1
			MISSING_ELSE
165	1	1
166	1	1
170	1	1
171	1	1
174	1	1
175	1	1
178	1	1
180	1	1
185	1	1
187	1	1
188	1	1
192	1	1
193	1	1
197	1	1
198	1	1
202	1	1
203	1	1
214	1	1
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
221	1	1
222	1	1
235	1	1
236	1	1
238	1	1
243	1	1
245	1	1
246	1	1
248	1	1
250	1	1
251	1	1
253	1	1
258	1	1
259	1	1
261	1	1
262	1	1
264	1	1
266	1	1
267	1	1
279	1	1
283	1	1
291		unreachable
294	1	1
295	1	1
296	1	1
299		unreachable

---

Cond Coverage for Module : prim_packer

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       82
 EXPRESSION ((int'(pos_q) <= OutW) ? '0 : ((pos_q - 8'(OutW))))
             ----------1----------

-1-	Status	Tests
0	Unreachable	T1,T2,T12
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION ((int'(pos_with_input) <= OutW) ? '0 : ((pos_with_input - 8'(OutW))))
             ---------------1--------------

-1-	Status	Tests
0	Unreachable	T2,T12,T13
1	Covered	T25,T26,T67

 LINE       159
 EXPRESSION (mask_i[i] == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       165
 EXPRESSION (valid_i & ready_o)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable	T18,T4,T36
1	1	Covered	T1,T2,T3

 LINE       166
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T36,T25
1	1	Covered	T1,T2,T3

 LINE       170
 EXPRESSION (valid_i ? ((data_i >> lod_idx)) : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       171
 EXPRESSION (valid_i ? ((mask_i >> lod_idx)) : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       258
 EXPRESSION (pos_q == '0)
            ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       283
 EXPRESSION ((int'(pos_q) >= OutW) ? 1'b1 : flush_valid)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Unreachable	T1,T2,T3

---

Branch Coverage for Module : prim_packer

	Line No.	Total	Covered	Percent
Branches		30	27	90.00
TERNARY	170	2	2	100.00
TERNARY	171	2	2	100.00
TERNARY	283	1	1	100.00
IF	159	2	2	100.00
CASE	185	5	4	80.00
IF	214	3	3	100.00
IF	235	2	2	100.00
CASE	248	5	4	80.00
CASE	80	5	4	80.00
IF	90	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	170	(valid_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	171	(valid_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	283	((int'(pos_q) >= OutW)) ? 

Branches:

-1-	Status	Tests
1	Unreachable	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	159	if ((mask_i[i] == 1'b1))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	185	case ({ack_in, ack_out})

Branches:

-1-	Status	Tests
2'b00	Covered	T1,T2,T3
2'b01	Covered	T1,T2,T3
2'b10	Covered	T1,T2,T3
2'b11	Covered	T2,T12,T13
default	Not Covered

	LineNo.	Expression
-1-:	214	if ((!rst_ni))
-2-:	217	if (flush_done)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	235	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	248	case (flush_st)
-2-:	250	if (flush_i)
-3-:	258	if ((pos_q == '0))

Branches:

-1-	-2-	-3-	Status	Tests
FlushIdle	1	-	Covered	T1,T2,T3
FlushIdle	0	-	Covered	T1,T2,T3
FlushSend	-	1	Covered	T1,T2,T3
FlushSend	-	0	Covered	T1,T2,T3
default	-	-	Not Covered

	LineNo.	Expression
-1-:	80	case ({ack_in, ack_out})
-2-:	82	((int'(pos_q) <= OutW)) ? 
-3-:	84	((int'(pos_with_input) <= OutW)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
2'b00	-	-	Covered	T1,T2,T3
2'b01	1	-	Covered	T1,T2,T3
2'b01	0	-	Unreachable	T1,T2,T12
2'b10	-	-	Covered	T1,T2,T3
2'b11	-	1	Covered	T25,T26,T67
2'b11	-	0	Unreachable	T2,T12,T13
default	-	-	Not Covered

	LineNo.	Expression
-1-:	90	if ((!rst_ni))
-2-:	92	if (flush_done)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_packer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	28	28	100.00	28	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	28	28	100.00	28	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataIStable_M	1483890336	131243	0	948
DataOStableWhenPending_A	1483890336	124077	0	948
ExFlushValid_M	1483890336	208193	0	0
ExcessiveDataStored_A	1483890336	63138	0	0
ExcessiveMaskStored_A	1483890336	63138	0	0
FlushFollowedByDone_A	1483890336	208193	0	948
ValidIDeassertedOnFlush_M	1483890336	349659	0	0
ValidOAssertedForStoredDataGTEOutW_A	1483890336	33707903	0	0
ValidOPairedWidthReadyI_A	1483890336	124077	0	0
g_byte_assert.InputDividedBy8_A	948	948	0	0
g_byte_assert.OutputDividedBy8_A	948	948	0	0
g_byte_assert.g_byte_input_masking[0].InputMaskContiguous_A	1483890336	76362537	0	0
g_byte_assert.g_byte_input_masking[1].InputMaskContiguous_A	1483890336	76362537	0	0
g_byte_assert.g_byte_input_masking[2].InputMaskContiguous_A	1483890336	76362537	0	0
g_byte_assert.g_byte_input_masking[3].InputMaskContiguous_A	1483890336	76362537	0	0
g_byte_assert.g_byte_input_masking[4].InputMaskContiguous_A	1483890336	76362537	0	0
g_byte_assert.g_byte_input_masking[5].InputMaskContiguous_A	1483890336	76362537	0	0
g_byte_assert.g_byte_input_masking[6].InputMaskContiguous_A	1483890336	76362537	0	0
g_byte_assert.g_byte_input_masking[7].InputMaskContiguous_A	1483890336	76362537	0	0
g_byte_assert.g_byte_output_masking[0].OutputMaskContiguous_A	1483890336	33847359	0	0
g_byte_assert.g_byte_output_masking[1].OutputMaskContiguous_A	1483890336	33847359	0	0
g_byte_assert.g_byte_output_masking[2].OutputMaskContiguous_A	1483890336	33847359	0	0
g_byte_assert.g_byte_output_masking[3].OutputMaskContiguous_A	1483890336	33847359	0	0
g_byte_assert.g_byte_output_masking[4].OutputMaskContiguous_A	1483890336	33847359	0	0
g_byte_assert.g_byte_output_masking[5].OutputMaskContiguous_A	1483890336	33847359	0	0
g_byte_assert.g_byte_output_masking[6].OutputMaskContiguous_A	1483890336	33847359	0	0
g_byte_assert.g_byte_output_masking[7].OutputMaskContiguous_A	1483890336	33847359	0	0
gen_mask_assert.ContiguousOnesMask_M	1483890336	76362537	0	0

DataIStable_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1483890336	131243	0	948
T4	5228	40	0	1
T18	126030	5	0	1
T22	294917	0	0	1
T23	0	124	0	0
T25	0	350	0	0
T26	0	1008	0	0
T27	0	1	0	0
T28	291431	0	0	1
T36	0	954	0	0
T43	823	0	0	1
T67	0	2374	0	0
T73	0	141	0	0
T80	178105	0	0	1
T81	52172	0	0	1
T82	505821	0	0	1
T83	71909	0	0	1
T84	650076	0	0	1
T100	0	12	0	0

DataOStableWhenPending_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1483890336	124077	0	948
T4	5228	3721	0	1
T5	222205	0	0	1
T6	70781	0	0	1
T23	102263	45	0	1
T25	163258	43	0	1
T26	0	443	0	0
T27	111606	0	0	1
T29	0	1062	0	0
T36	809384	1013	0	1
T43	823	0	0	1
T67	0	1669	0	0
T73	0	141	0	0
T85	470780	0	0	1
T101	0	265	0	0
T102	0	2630	0	0
T103	184342	0	0	1

ExFlushValid_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1483890336	208193	0	0
T1	7879	3	0	0
T2	496457	191	0	0
T3	6670	9	0	0
T12	725361	83	0	0
T13	536958	198	0	0
T14	648743	390	0	0
T15	945150	129	0	0
T16	142370	110	0	0
T17	167837	181	0	0
T18	126030	114	0	0

ExcessiveDataStored_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1483890336	63138	0	0
T2	496457	36	0	0
T3	6670	0	0	0
T4	0	26	0	0
T12	725361	6	0	0
T13	536958	28	0	0
T14	648743	0	0	0
T15	945150	1	0	0
T16	142370	0	0	0
T17	167837	5	0	0
T18	126030	4	0	0
T22	294917	4	0	0
T28	0	2	0	0
T36	0	624	0	0

ExcessiveMaskStored_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1483890336	63138	0	0
T2	496457	36	0	0
T3	6670	0	0	0
T4	0	26	0	0
T12	725361	6	0	0
T13	536958	28	0	0
T14	648743	0	0	0
T15	945150	1	0	0
T16	142370	0	0	0
T17	167837	5	0	0
T18	126030	4	0	0
T22	294917	4	0	0
T28	0	2	0	0
T36	0	624	0	0

FlushFollowedByDone_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1483890336	208193	0	948
T1	7879	3	0	1
T2	496457	191	0	1
T3	6670	9	0	1
T12	725361	83	0	1
T13	536958	198	0	1
T14	648743	390	0	1
T15	945150	129	0	1
T16	142370	110	0	1
T17	167837	181	0	1
T18	126030	114	0	1

ValidIDeassertedOnFlush_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1483890336	349659	0	0
T1	7879	6	0	0
T2	496457	332	0	0
T3	6670	18	0	0
T12	725361	151	0	0
T13	536958	353	0	0
T14	648743	730	0	0
T15	945150	236	0	0
T16	142370	208	0	0
T17	167837	335	0	0
T18	126030	215	0	0

ValidOAssertedForStoredDataGTEOutW_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1483890336	33707903	0	0
T1	7879	176	0	0
T2	496457	10643	0	0
T3	6670	100	0	0
T12	725361	4478	0	0
T13	536958	12434	0	0
T14	648743	95772	0	0
T15	945150	7568	0	0
T16	142370	69496	0	0
T17	167837	10496	0	0
T18	126030	7789	0	0

ValidOPairedWidthReadyI_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1483890336	124077	0	0
T4	5228	3721	0	0
T5	222205	0	0	0
T6	70781	0	0	0
T23	102263	45	0	0
T25	163258	43	0	0
T26	0	443	0	0
T27	111606	0	0	0
T29	0	1062	0	0
T36	809384	1013	0	0
T43	823	0	0	0
T67	0	1669	0	0
T73	0	141	0	0
T85	470780	0	0	0
T101	0	265	0	0
T102	0	2630	0	0
T103	184342	0	0	0

g_byte_assert.InputDividedBy8_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	948	948	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

g_byte_assert.OutputDividedBy8_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	948	948	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

g_byte_assert.g_byte_input_masking[0].InputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1483890336	76362537	0	0
T1	7879	406	0	0
T2	496457	19869	0	0
T3	6670	214	0	0
T12	725361	9079	0	0
T13	536958	23699	0	0
T14	648743	223052	0	0
T15	945150	17364	0	0
T16	142370	159916	0	0
T17	167837	23646	0	0
T18	126030	18827	0	0

g_byte_assert.g_byte_input_masking[1].InputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1483890336	76362537	0	0
T1	7879	406	0	0
T2	496457	19869	0	0
T3	6670	214	0	0
T12	725361	9079	0	0
T13	536958	23699	0	0
T14	648743	223052	0	0
T15	945150	17364	0	0
T16	142370	159916	0	0
T17	167837	23646	0	0
T18	126030	18827	0	0

g_byte_assert.g_byte_input_masking[2].InputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1483890336	76362537	0	0
T1	7879	406	0	0
T2	496457	19869	0	0
T3	6670	214	0	0
T12	725361	9079	0	0
T13	536958	23699	0	0
T14	648743	223052	0	0
T15	945150	17364	0	0
T16	142370	159916	0	0
T17	167837	23646	0	0
T18	126030	18827	0	0

g_byte_assert.g_byte_input_masking[3].InputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1483890336	76362537	0	0
T1	7879	406	0	0
T2	496457	19869	0	0
T3	6670	214	0	0
T12	725361	9079	0	0
T13	536958	23699	0	0
T14	648743	223052	0	0
T15	945150	17364	0	0
T16	142370	159916	0	0
T17	167837	23646	0	0
T18	126030	18827	0	0

g_byte_assert.g_byte_input_masking[4].InputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1483890336	76362537	0	0
T1	7879	406	0	0
T2	496457	19869	0	0
T3	6670	214	0	0
T12	725361	9079	0	0
T13	536958	23699	0	0
T14	648743	223052	0	0
T15	945150	17364	0	0
T16	142370	159916	0	0
T17	167837	23646	0	0
T18	126030	18827	0	0

g_byte_assert.g_byte_input_masking[5].InputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1483890336	76362537	0	0
T1	7879	406	0	0
T2	496457	19869	0	0
T3	6670	214	0	0
T12	725361	9079	0	0
T13	536958	23699	0	0
T14	648743	223052	0	0
T15	945150	17364	0	0
T16	142370	159916	0	0
T17	167837	23646	0	0
T18	126030	18827	0	0

g_byte_assert.g_byte_input_masking[6].InputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1483890336	76362537	0	0
T1	7879	406	0	0
T2	496457	19869	0	0
T3	6670	214	0	0
T12	725361	9079	0	0
T13	536958	23699	0	0
T14	648743	223052	0	0
T15	945150	17364	0	0
T16	142370	159916	0	0
T17	167837	23646	0	0
T18	126030	18827	0	0

g_byte_assert.g_byte_input_masking[7].InputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1483890336	76362537	0	0
T1	7879	406	0	0
T2	496457	19869	0	0
T3	6670	214	0	0
T12	725361	9079	0	0
T13	536958	23699	0	0
T14	648743	223052	0	0
T15	945150	17364	0	0
T16	142370	159916	0	0
T17	167837	23646	0	0
T18	126030	18827	0	0

g_byte_assert.g_byte_output_masking[0].OutputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1483890336	33847359	0	0
T1	7879	179	0	0
T2	496457	10784	0	0
T3	6670	109	0	0
T12	725361	4546	0	0
T13	536958	12589	0	0
T14	648743	96112	0	0
T15	945150	7675	0	0
T16	142370	69594	0	0
T17	167837	10650	0	0
T18	126030	7890	0	0

g_byte_assert.g_byte_output_masking[1].OutputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1483890336	33847359	0	0
T1	7879	179	0	0
T2	496457	10784	0	0
T3	6670	109	0	0
T12	725361	4546	0	0
T13	536958	12589	0	0
T14	648743	96112	0	0
T15	945150	7675	0	0
T16	142370	69594	0	0
T17	167837	10650	0	0
T18	126030	7890	0	0

g_byte_assert.g_byte_output_masking[2].OutputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1483890336	33847359	0	0
T1	7879	179	0	0
T2	496457	10784	0	0
T3	6670	109	0	0
T12	725361	4546	0	0
T13	536958	12589	0	0
T14	648743	96112	0	0
T15	945150	7675	0	0
T16	142370	69594	0	0
T17	167837	10650	0	0
T18	126030	7890	0	0

g_byte_assert.g_byte_output_masking[3].OutputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1483890336	33847359	0	0
T1	7879	179	0	0
T2	496457	10784	0	0
T3	6670	109	0	0
T12	725361	4546	0	0
T13	536958	12589	0	0
T14	648743	96112	0	0
T15	945150	7675	0	0
T16	142370	69594	0	0
T17	167837	10650	0	0
T18	126030	7890	0	0

g_byte_assert.g_byte_output_masking[4].OutputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1483890336	33847359	0	0
T1	7879	179	0	0
T2	496457	10784	0	0
T3	6670	109	0	0
T12	725361	4546	0	0
T13	536958	12589	0	0
T14	648743	96112	0	0
T15	945150	7675	0	0
T16	142370	69594	0	0
T17	167837	10650	0	0
T18	126030	7890	0	0

g_byte_assert.g_byte_output_masking[5].OutputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1483890336	33847359	0	0
T1	7879	179	0	0
T2	496457	10784	0	0
T3	6670	109	0	0
T12	725361	4546	0	0
T13	536958	12589	0	0
T14	648743	96112	0	0
T15	945150	7675	0	0
T16	142370	69594	0	0
T17	167837	10650	0	0
T18	126030	7890	0	0

g_byte_assert.g_byte_output_masking[6].OutputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1483890336	33847359	0	0
T1	7879	179	0	0
T2	496457	10784	0	0
T3	6670	109	0	0
T12	725361	4546	0	0
T13	536958	12589	0	0
T14	648743	96112	0	0
T15	945150	7675	0	0
T16	142370	69594	0	0
T17	167837	10650	0	0
T18	126030	7890	0	0

g_byte_assert.g_byte_output_masking[7].OutputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1483890336	33847359	0	0
T1	7879	179	0	0
T2	496457	10784	0	0
T3	6670	109	0	0
T12	725361	4546	0	0
T13	536958	12589	0	0
T14	648743	96112	0	0
T15	945150	7675	0	0
T16	142370	69594	0	0
T17	167837	10650	0	0
T18	126030	7890	0	0

gen_mask_assert.ContiguousOnesMask_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1483890336	76362537	0	0
T1	7879	406	0	0
T2	496457	19869	0	0
T3	6670	214	0	0
T12	725361	9079	0	0
T13	536958	23699	0	0
T14	648743	223052	0	0
T15	945150	17364	0	0
T16	142370	159916	0	0
T17	167837	23646	0	0
T18	126030	18827	0	0