Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1485369414	64114	0	0
entropy_period_rd_A	1485369414	1958	0	0
intr_enable_rd_A	1485369414	2885	0	0
prefix_0_rd_A	1485369414	2128	0	0
prefix_10_rd_A	1485369414	2175	0	0
prefix_1_rd_A	1485369414	2302	0	0
prefix_2_rd_A	1485369414	2270	0	0
prefix_3_rd_A	1485369414	2121	0	0
prefix_4_rd_A	1485369414	2290	0	0
prefix_5_rd_A	1485369414	2210	0	0
prefix_6_rd_A	1485369414	2137	0	0
prefix_7_rd_A	1485369414	2233	0	0
prefix_8_rd_A	1485369414	2307	0	0
prefix_9_rd_A	1485369414	1995	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1485369414	64114	0	0
T32	333080	43760	0	0
T46	0	17006	0	0
T47	0	88	0	0
T57	76190	0	0	0
T58	30022	0	0	0
T104	0	2	0	0
T105	0	3	0	0
T106	0	3	0	0
T107	0	179	0	0
T111	0	152	0	0
T114	0	1	0	0
T115	0	3	0	0
T118	718681	0	0	0
T119	780910	0	0	0
T120	23564	0	0	0
T121	247844	0	0	0
T122	248177	0	0	0
T123	21826	0	0	0
T124	431812	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1485369414	1958	0	0
T46	261992	48	0	0
T89	0	46	0	0
T99	0	3	0	0
T114	0	12	0	0
T116	0	22	0	0
T137	0	16	0	0
T138	0	104	0	0
T139	0	4	0	0
T140	0	3	0	0
T141	0	6	0	0
T142	1752	0	0	0
T143	215483	0	0	0
T144	6088	0	0	0
T145	110644	0	0	0
T146	99176	0	0	0
T147	596390	0	0	0
T148	16960	0	0	0
T149	189660	0	0	0
T150	183599	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1485369414	2885	0	0
T46	261992	52	0	0
T107	0	2	0	0
T108	0	22	0	0
T109	0	21	0	0
T114	0	33	0	0
T137	0	17	0	0
T138	0	199	0	0
T139	0	15	0	0
T142	1752	0	0	0
T143	215483	0	0	0
T144	6088	0	0	0
T145	110644	0	0	0
T146	99176	0	0	0
T147	596390	0	0	0
T148	16960	0	0	0
T149	189660	0	0	0
T150	183599	0	0	0
T151	0	18	0	0
T152	0	20	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1485369414	2128	0	0
T46	261992	40	0	0
T89	0	42	0	0
T99	0	10	0	0
T114	0	18	0	0
T116	0	18	0	0
T137	0	13	0	0
T138	0	206	0	0
T139	0	2	0	0
T140	0	8	0	0
T141	0	13	0	0
T142	1752	0	0	0
T143	215483	0	0	0
T144	6088	0	0	0
T145	110644	0	0	0
T146	99176	0	0	0
T147	596390	0	0	0
T148	16960	0	0	0
T149	189660	0	0	0
T150	183599	0	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1485369414	2175	0	0
T46	261992	52	0	0
T89	0	28	0	0
T99	0	5	0	0
T114	0	19	0	0
T116	0	33	0	0
T137	0	7	0	0
T138	0	231	0	0
T139	0	4	0	0
T140	0	6	0	0
T141	0	10	0	0
T142	1752	0	0	0
T143	215483	0	0	0
T144	6088	0	0	0
T145	110644	0	0	0
T146	99176	0	0	0
T147	596390	0	0	0
T148	16960	0	0	0
T149	189660	0	0	0
T150	183599	0	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1485369414	2302	0	0
T46	261992	44	0	0
T89	0	38	0	0
T99	0	18	0	0
T114	0	23	0	0
T116	0	23	0	0
T137	0	8	0	0
T138	0	266	0	0
T139	0	3	0	0
T140	0	4	0	0
T141	0	7	0	0
T142	1752	0	0	0
T143	215483	0	0	0
T144	6088	0	0	0
T145	110644	0	0	0
T146	99176	0	0	0
T147	596390	0	0	0
T148	16960	0	0	0
T149	189660	0	0	0
T150	183599	0	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1485369414	2270	0	0
T46	261992	69	0	0
T89	0	25	0	0
T99	0	1	0	0
T114	0	15	0	0
T116	0	37	0	0
T137	0	14	0	0
T138	0	234	0	0
T139	0	1	0	0
T140	0	7	0	0
T141	0	7	0	0
T142	1752	0	0	0
T143	215483	0	0	0
T144	6088	0	0	0
T145	110644	0	0	0
T146	99176	0	0	0
T147	596390	0	0	0
T148	16960	0	0	0
T149	189660	0	0	0
T150	183599	0	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1485369414	2121	0	0
T46	261992	43	0	0
T89	0	17	0	0
T99	0	5	0	0
T114	0	18	0	0
T116	0	12	0	0
T137	0	16	0	0
T138	0	216	0	0
T139	0	2	0	0
T140	0	3	0	0
T141	0	16	0	0
T142	1752	0	0	0
T143	215483	0	0	0
T144	6088	0	0	0
T145	110644	0	0	0
T146	99176	0	0	0
T147	596390	0	0	0
T148	16960	0	0	0
T149	189660	0	0	0
T150	183599	0	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1485369414	2290	0	0
T46	261992	76	0	0
T89	0	30	0	0
T99	0	7	0	0
T114	0	17	0	0
T116	0	4	0	0
T137	0	4	0	0
T138	0	222	0	0
T139	0	9	0	0
T140	0	8	0	0
T141	0	7	0	0
T142	1752	0	0	0
T143	215483	0	0	0
T144	6088	0	0	0
T145	110644	0	0	0
T146	99176	0	0	0
T147	596390	0	0	0
T148	16960	0	0	0
T149	189660	0	0	0
T150	183599	0	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1485369414	2210	0	0
T46	261992	43	0	0
T89	0	41	0	0
T99	0	5	0	0
T114	0	11	0	0
T116	0	24	0	0
T137	0	12	0	0
T138	0	262	0	0
T139	0	2	0	0
T140	0	6	0	0
T141	0	3	0	0
T142	1752	0	0	0
T143	215483	0	0	0
T144	6088	0	0	0
T145	110644	0	0	0
T146	99176	0	0	0
T147	596390	0	0	0
T148	16960	0	0	0
T149	189660	0	0	0
T150	183599	0	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1485369414	2137	0	0
T46	261992	56	0	0
T89	0	28	0	0
T99	0	12	0	0
T114	0	14	0	0
T116	0	22	0	0
T137	0	15	0	0
T138	0	250	0	0
T139	0	2	0	0
T140	0	1	0	0
T141	0	12	0	0
T142	1752	0	0	0
T143	215483	0	0	0
T144	6088	0	0	0
T145	110644	0	0	0
T146	99176	0	0	0
T147	596390	0	0	0
T148	16960	0	0	0
T149	189660	0	0	0
T150	183599	0	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1485369414	2233	0	0
T46	261992	35	0	0
T89	0	31	0	0
T91	0	57	0	0
T99	0	11	0	0
T114	0	14	0	0
T116	0	18	0	0
T137	0	7	0	0
T138	0	235	0	0
T140	0	8	0	0
T141	0	2	0	0
T142	1752	0	0	0
T143	215483	0	0	0
T144	6088	0	0	0
T145	110644	0	0	0
T146	99176	0	0	0
T147	596390	0	0	0
T148	16960	0	0	0
T149	189660	0	0	0
T150	183599	0	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1485369414	2307	0	0
T46	261992	43	0	0
T89	0	33	0	0
T99	0	5	0	0
T114	0	14	0	0
T116	0	32	0	0
T137	0	10	0	0
T138	0	229	0	0
T139	0	8	0	0
T140	0	9	0	0
T141	0	10	0	0
T142	1752	0	0	0
T143	215483	0	0	0
T144	6088	0	0	0
T145	110644	0	0	0
T146	99176	0	0	0
T147	596390	0	0	0
T148	16960	0	0	0
T149	189660	0	0	0
T150	183599	0	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1485369414	1995	0	0
T46	261992	74	0	0
T89	0	25	0	0
T99	0	9	0	0
T114	0	13	0	0
T116	0	15	0	0
T137	0	4	0	0
T138	0	183	0	0
T139	0	8	0	0
T140	0	2	0	0
T141	0	3	0	0
T142	1752	0	0	0
T143	215483	0	0	0
T144	6088	0	0	0
T145	110644	0	0	0
T146	99176	0	0	0
T147	596390	0	0	0
T148	16960	0	0	0
T149	189660	0	0	0
T150	183599	0	0	0