| SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING | 
| 100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 | 
| NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING | 
| mubi4_cov_of_mubi4_cov_of_tb.dut.kmac_sha3_absorb_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 | 
| mubi4_cov_of_mubi4_cov_of_tb.dut.kmac_sha3_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 | 
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING | 
| 100.00 | 1 | 100 | 1 | 64 | 64 | 
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 6 | 0 | 6 | 100.00 | 
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 | 
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING | 
| 100.00 | 1 | 100 | 1 | 64 | 64 | 
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 6 | 0 | 6 | 100.00 | 
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 | 
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 6 | 0 | 6 | 100.00 | 
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| others[0] | 565 | 1 | T3 | 10 | T4 | 1 | T14 | 30 | ||||
| others[1] | 538 | 1 | T3 | 15 | T14 | 33 | T16 | 9 | ||||
| others[2] | 552 | 1 | T3 | 14 | T4 | 1 | T14 | 39 | ||||
| others[3] | 960 | 1 | T3 | 13 | T4 | 2 | T14 | 44 | ||||
| false | 189480 | 1 | T1 | 1 | T2 | 375 | T3 | 442 | ||||
| true | 186716 | 1 | T2 | 374 | T3 | 434 | T4 | 312 | 
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 6 | 0 | 6 | 100.00 | 
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| others[0] | 846 | 1 | T3 | 16 | T4 | 1 | T14 | 39 | ||||
| others[1] | 582 | 1 | T3 | 7 | T4 | 3 | T14 | 32 | ||||
| others[2] | 548 | 1 | T3 | 10 | T14 | 25 | T16 | 11 | ||||
| others[3] | 960 | 1 | T3 | 19 | T14 | 50 | T16 | 23 | ||||
| false | 189797 | 1 | T1 | 1 | T2 | 375 | T3 | 442 | ||||
| true | 186712 | 1 | T2 | 374 | T3 | 434 | T4 | 312 | 
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |